The rapid evolution of memory technologies and the advent of Compute Express Link (CXL) have opened up new possibilities for scaling main memory by enabling hybrid memory systems with pooled and shared content. System-level evaluation of new memory systems during the early development stage is important for the enablement and further integration of new memory and interconnect technologies. However, existing solutions do not offer a framework neither for emerging memory protocols nor for novel memory technologies. This paper introduces CXL-HMEM to evaluate emerging CXL-based hybrid main memory architectures by applying the System Technology Co-Optimization (STCO) technique. The framework provides flexible performance metrics, workload simulation, and memory traffic analysis to assess system performance under various hybrid memory configurations, including DRAM and tiered memory hierarchies. Key features include support for memory technologies such as IGZO-based DRAM (IGZO) and FeRAM, workload scalability, and an integrated model of the CXL behavior. CXL-HMEM shows that emerging memories can improve system bandwidth and energy consumption by 7%, while having potential to further mitigate particular bottlenecks. CXL-based hybrid main memory can speed up the memory access time by >2× compared to conventional approaches of main memory extension.

The demand for high-capacity and energy-efficient memory solutions has surged in the era of data-centric computing, particularly for Artificial Intelligence (AI) and Machine Learning (ML) workloads. This paper introduces a novel memory architecture leveraging Charge-Coupled Device (CCD) technology, engineered in a sequential-access block memory configuration, to enhance Compute-near-Memory (CnM) systems. We propose an optimized 3D IGZO CCD block memory as an on-chip weight buffer for high-capacity CnM systems. Our approach achieves 2.95−131.26× improvement in area efficiency and 1.32−4.33× improvement in energy efficiency compared to SRAM solutions.

To continue increasing the storage density of 3D NAND flash memories, new technology options need to be evaluated early on. This work presents a unique predictive parametric framework for Multi-Level Cell 3D NAND Flash read operation at the array level. This framework is used to explore the read sensitivity to multiple parameters and technology options. We identify the trade-offs between number of layers, read-current and read time to be the most determinant factors to ensure the array readability while enabling stacks of more than 300 layers and maximizing the memory density.

This paper plans to implement the benefit of deep hybrid learning for fingerprint liveness detection. The fingerprint image is subjected to background removal using Active contour. Further, the feature extraction is performed by the optimized Scale-Invariant Feature Transform (SIFT) and hybrid feature descriptor. New Modified Shark Smell Optimization (M-SSO) is used for developing optimized SIFT keypoints. The hybridization of the Local Directional Pattern (LDP) and Local Binary Pattern (LBP) is used as the feature pattern extraction. The classification phase combines Recurrent Neural Network (RNN) and Convolutional Neural Network (CNN). The optimized SIFT keypoints are taken as input by RNN, and the patterns resulting from hybrid LDP and LBP are taken as input by CNN. The M-SSO optimizes the number of hidden neurons of both RNN and CNN to maximize classification accuracy. The proposed approach significantly improves the performance of FLD on different benchmark datasets over state-of-the-art models.