This article presents a power-efficient echo-cancellation-based hybrid architecture for full-duplex (FD) chip-to-chip interconnects. Conventional FD transceivers employ three separate transconductance stages for signal transmission, replica generation, and signal separation, thereby increasing overall power consumption (PC). The proposed hybrid topology reduces this overhead by integrating a linear resistor within the replica driver (RD) for retrieving the incoming signal from the tri-level superimposed signal at the transceiver interface. This makes the proposed hybrid power-efficient compared to the existing FD hybrid circuit topologies. The prototype design has been fabricated in 1.2-V, 65-nm CMOS technology. The measured results of the proposed hybrid circuit have a received signal with an eye-opening of 20 mV at a data rate of 8 Gb/s over a 20-cm FR4 PCB trace. The proposed hybrid achieves a PC of only 0.3mW and an energy efficiency of 0.075 pJ/bit. The active silicon area occupied by the hybrid is$0.0045~\mathrm {mm}^{2}$.

The transparency property of the N-path mixers made the mixer-first RF front-ends to operate over wide frequency range with tunable impedance matching. However, the requirement of non-overlapping clocks for the RF-sampling N-path mixer causes the power consumption of the clock generation to overwhelm the receiver power consumption. Contrary to RF-sampling mixers, sub-harmonic mixers operating at low clock frequencies save the power consumption of clocking circuitry. However, sub-harmonic mixers are limited to operate at harmonic order of less than N/2 for N-path mixer-first RF front-ends due to their dependency on the number of mixer paths for impedance matching at the RF port. To address this issue, in this work, a novel impedance matching scheme by synthesizing a negative baseband impedance is proposed to facilitate the impedance matching at the desired higher-order harmonic of the sampling frequency. The proposed scheme breaks the tradeoff between the number of paths of the mixer, harmonic order and impedance matching of N-path mixer-first RF front-ends. Also, this work presents a design example using the proposed technique, operating at harmonic order greater than N/2 to validate the proposed idea.

Received signal strength indicator (RSSI) is indispensable in modern wireless communications for detecting and measuring signal strength. This paper presents a new RSSI system architecture that addresses the constraints of conventional designs. Traditional RSSI systems implemented at the RF level encounter challenges such as limited dynamic range and impedance matching, while baseband implementations contend with high power consumption and depend on analog-to-digital converters (ADCs) to digitize signal strength. Moreover, the large dynamic range necessitates high-resolution ADCs, which further exacerbates area and power consumption. The proposed RSSI architecture at baseband mitigates these challenges by employing a limiting amplifier, followed by a peak detector and comparator at each stage, thus eliminating the need for an ADC. This configuration enables coarse control and provides the most significant bits (MSBs) of the RSSI. Additionally, a programmable gain amplifier in conjunction with an up-counter captures the least significant bits (LSBs) of the RSSI, providing fine control. The system is implemented in a 65 nm CMOS process, operating at 1.2 V, with a power consumption of 256 μW. It achieves a wide dynamic range of 80-dB and a detection accuracy of ±0.6 dB, as validated through detailed simulations.

Subsampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the subsampling down-conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF port by impedance translation. In this work, an eight-path quarter-rate subsampling (QRSS) mixer-first direct down-conversion architecture is proposed to address these issues. The proposed architecture simultaneously achieves quadrature direct down-conversion and impedance matching by using the third harmonic of the QRSS frequency,$f_s$. The impedance matching is achieved by exploiting the eight-path passive mixer transparency property. Compared to RF sampling receivers, this architecture employs a sampling frequency$f_s$three times lesser than$f_{\text{RF}}$, saving on the power consumption of nonoverlapping clock generation, distribution circuits, and frequency synthesizer. A test chip is fabricated in 1.2-V, 65-nm CMOS with an active area of 0.32 mm$^2$. The subsampling eight-path mixer, baseband low-noise amplifier (LNA), and g$_m$-cell consume a power of 800$\mu$W, 23 mW, and 3 mW, respectively, for a target bandwidth of 90 MHz. Nonoverlapping clock generation circuit consumes 2–9.2 mW, over the band 0.4–1.8 GHz. The receiver has a double sideband (DSB) noise figure of 4.7 dB, a conversion gain of 22 dB, an in-band (IB)-IIP$_3$of$-$1 dBm, and OB-IIP$_3$of$+$8 dBm.

Reconfigurable subsampling mixer-first RF front-end is a potential candidate for low-power applications as it operates at a low clock frequency and hence consumes low power. However, the subsampling down-conversion has not been employed in mixer-first RF front-ends due to the disadvantage of high noise figure from inherent noise folding and lack of RF port impedance matching because of nonzero IF down-conversion. To address the above two issues, first, a subsampling multipath down-conversion mixer scheme is proposed for rejecting$3f_{s}/4$and$5f_{s}/4$down-conversions, thereby alleviating the effect of noise folding, leading to low noise figure. Second, an IF-stage impedance matching scheme is proposed that provides$50~\Omega $matching at the RF port of the mixer using an IF-LNA in shunt with an$M$-phase switch-capacitor filter. The analysis of the proposed scheme in terms of noise figure, conversion gain, and harmonic rejection is presented. The proposed subsampling mixer-first RF front-end is implemented in 1.2 V, 65-nm CMOS technology. The prototype occupies an active area of 0.33 mm2, the switch-capacitor mixer and$M$-phase filter consume$400~\mu \text{W}$of power, and IF amplifier and nonoverlapping clock generation circuit consume 25 mW and 6–12.6 mW of power, respectively. The RF front-end achieves a 6.5-dB noise figure, 15.1-dB conversion gain, 50-dB harmonic rejection ratio (HRR), and +10-dBm IB-IIP3.