The post-silicon integrated circuits (IC) testing is a very expensive process, especially in automotive industry where chip functionality has to be guaranteed by verifying multiple electrical parameters over a wide range of operating conditions. However, some costs can be avoided by reducing the amount of redundant tests, as certain parameters may exhibit a predictable behavior on the operating conditions variation. This paper presents a comparison between three approaches that use temperature parameters behavior for reducing the number of IC tests. The methods are tested on a production dataset consisting of 25 parameters and 300000 chips, results showing that the best method saves approximately 12 % of the measurements.

This paper introduces several solutions for multivariate extension of a previously designed single response adaptive pre-silicon integrated circuit verification approach employing machine learning algorithms. These techniques aim to achieve the most accurate identification of worst-case circuit behavior through simultaneously modeling multiple electrical parameters (EP). The effectiveness of the proposed methods was validated through extensive testing on a large and diverse set of synthetic test functions that intend to replicate the behavior of real circuits. The algorithms consistency and accuracy are also validated on a real Low Dropout Voltage Regulator (LDO) circuit.

There is a consistent dependence between integrated circuits (ICs) performance parameters and manufacturing process variations and capturing it at an early development phase represents a major ongoing topic in the semiconductor industry. Typically, this is addressed by the means of Monte Carlo (MC) simulations, where the device model parameters are randomly instantiated according to the technology variations based on a predefined nominal process. Thus, the resulted simulation data can only capture the effect of these variations. This offers little or no insight on the performance’s sensitivities to specific process variations or on the effect of altered statistical technology properties, as it may be the case of process drift or fab-to-fab migration. This article proposes a methodology for modeling the dependency of the device performances (i.e., electrical parameters—EPs) with the influential technology parameters (i.e., process control monitor parameters—PCMs), at an early stage (preSilicon). Using a set of standard MC co-simulations of PCM structures and the circuit schematics (to maintain consistent process variation), it employs a feature selection step to choose the influential PCMs and it trains a machine learning regression algorithm. Both are wrapped up in a Bayesian optimization (BO) framework to find the optimal feature set and the regression hyperparameters. The obtained regression model can explain the functional dependency of the EP on the influential PCMs. Thus, it directly enables sensitivity analysis (SA) to process variation and parametric yield prediction of the IC, as it will be illustrated for the case of an experimental Infineon Technologies product.

This paper proposes a pole-placement method for tuning the discrete PID control of a DC-DC Buck converter that ensure specific time-domain performances when a step disturbance in the input voltage or load is applied. The control is also designed to reduce steady-state oscillations caused by the digital implementation nonlinearities of the control loop. The effectiveness of the method is verified on both simulation and experimental levels.

This paper proposes a method for speeding-up the verification process of integrated circuits, featuring waveform clustering of circuit response signals. The main objective is to automatically separate the signals into distinct groups that potentially exhibit visual similarities in order to aid the visual inspection/verification. As a first step, the proposed method extracts SIFT-like features by finding stable points of the signal over the scale space and computing robust descriptors able to describe their neighborhood. The resulted descriptors are quantized in order to be used in the clustering process as bag-of-words histograms. We demonstrate the validity of our method on a circuit waveform database containing several thousands of signals belonging to ten electrical tests.