EDBT 2026 Demo / reviewers in the wild / expert
Divya Raghunathan
dblp:247/5971
· DBLP profile ↗
9ranked-venue papers
2as first author
7since 2021 · last 2026
0000-0003-0231-2086ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 4 · 1 first-author · 3 since 2021Software engineering, systems software and programming languages · 4 · 1 first-author · 3 since 2021Theory of computation · 4 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A Neurosymbolic Approach to Natural Language Formalization and VerificationabstractAbstract Large Language Models perform well at natural language interpretation and reasoning, but their lack of formal correctness guarantees limits their adoption in regulated industries like finance and healthcare that operate under strict policies. To address this limitation, we launched Automated Reasoning checks (ARc) : a public service that (1) uses LLMs with optional human guidance to formalize natural language policies, allowing fine-grained control of the formalization process, and (2) uses inference-time autoformalization to validate logical correctness of natural language statements against those policies. ARc performs multiple redundant formalization steps at inference time, checking the formalizations for semantic equivalence. Our benchmarks show that ARc exceeds 99% soundness and achieves a near-zero false positive rate in identifying logical validity. Our approach produces auditable artifacts that substantiate the verification outcomes and can be used to improve the original text. ARc is the first commercial offering from a major cloud provider to integrate automated reasoning into a generative AI guardrail. Chenyang An, Sam Bayless, Stefano Buliani, Darion Cassel, Byron Cook, Duncan Clough, Rémi Delmas, Nafi Diallo, Ferhat Erata, Nick Feng, Dimitra Giannakopoulou, Aman Goel, Aditya Gokhale, Joe Hendrix, Victor Heorhiadi, Marc Hudak, Dejan Jovanovic, Andrew M. Kent, Benjamin Kiesl-Reiter, Jeffrey J. Kuna, Nadia Labai, Joe Lilien, Divya Raghunathan, Zvonimir Rakamaric, Niloofar Razavi, Michael Tautschnig, Ali Torkamani, Nathaniel Weir, Michael W. Whalen, Jianan Yao |
CAV (2) | 23 |
| 2025 | A Layered Formal Methods Approach to Answering Queue-related Queries
Divya Raghunathan, Maria Apostolaki, Aarti Gupta |
NSDI | 1 |
| 2024 | Zoom2Net: Constrained Network Telemetry ImputationabstractFine-grained monitoring is crucial for multiple data-driven tasks such as debugging, provisioning, and securing networks. Yet, practical constraints in collecting, extracting, and storing data often force operators to use coarse-grained sampled monitoring, degrading the performance of the various tasks. In this work, we explore the feasibility of leveraging the correlations among coarse-grained time series to impute their fine-grained counterparts in software. We present Zoom2Net, a transformer-based model for network imputation that incorporates domain knowledge through operational and measurement constraints, ensuring that the imputed network telemetry time series are not only realistic but align with existing measurements. This approach enhances the capabilities of current monitoring infrastructures, allowing operators to gain more insights into system behaviors without the need for hardware upgrades. We evaluate Zoom2Net on four diverse datasets (e.g., cloud telemetry and Internet data transfer) and use cases (e.g., bursts analysis and traffic classification). We demonstrate that Zoom2Net consistently achieves high imputation accuracy with a zoom-in factor of up to 100 and performs better on downstream tasks compared to baselines by an average of 38%. Fengchen Gong, Divya Raghunathan, Aarti Gupta, Maria Apostolaki |
SIGCOMM | 2 |
| 2023 | CaT: A Solver-Aided Compiler for Packet-Processing PipelinesabstractCompiling high-level programs to high-speed packet-processing pipelines is a challenging combinatorial optimization problem. The compiler must configure the pipeline’s resources to match the semantics of the program’s high-level specification, while packing all of the program’s computation into the pipeline’s limited resources. State of the art approaches tackle individual aspects of this problem. Yet, they miss opportunities to produce globally high-quality outcomes within reasonable compilation times. We develop a framework to decompose the compilation problem for such pipelines into three phases—making extensive use of solver engines (e.g., ILP, SMT, and program synthesis) to simplify the development of these phases. Transformation rewrites programs to use more abundant pipeline resources, avoiding scarce ones. Synthesis breaks complex transactional code into configurations of pipelined compute units. Allocation maps the program’s compute and memory to the pipeline’s hardware resources. We prototype these ideas in a compiler, CaT, which targets (1) the Tofino programmable switch pipeline and (2) Menshen, a cycle-accurate simulator of a Verilog description of the RMT pipeline. CaT can handle programs that existing compilers cannot currently run on pipelines and generates code faster than existing compilers, where the generated code uses fewer pipeline resources. Divya Raghunathan, Ruijie Fang, Tao Wang 0088, Xiaotong Zhu, Anirudh Sivaraman, Srinivas Narayana, Aarti Gupta |
ASPLOS (3) | 2 |
| 2023 | Towards Integrating Formal Methods into ML-Based Systems for NetworkingabstractOwing to its adaptability and scalability, Machine Learning (ML) has gained significant momentum in the networking community. Yet, ML models can still produce outputs that contradict knowledge, i.e., established networking rules and principles. On the other hand, Formal Methods (FM) use rigorous mathematical reasoning based on knowledge, but suffer from the lack of scalability. To capitalize on the complementary strengths of both approaches, we advocate for the integration of knowledge-based FM into ML-based systems for networking problems. Through a case study, we demonstrate the benefits and limitations of using ML models or FM alone. We find that incorporating FM in the training and inference of an ML model yields not only more reliable results but also better performance in various downstream tasks. We hope that our paper inspires a tighter integration of FM-based and ML-based approaches in networking, facilitating the development of more robust and dependable systems. Fengchen Gong, Divya Raghunathan, Aarti Gupta, Maria Apostolaki |
HotNets | 2 |
| 2022 | ACORN: Network Control Plane Abstraction using Route Nondeterminism
Divya Raghunathan, Ryan Beckett, Aarti Gupta, David Walker 0001 |
FMCAD | 1 |
| 2022 | The Derby Game: An Ordering-based Colonel Blotto GameabstractThe Colonel Blotto game and its variants are a common approach to study competitive allocation of interchangeable resources (e.g., soldiers, money, or votes). We introduce a new variant of Blotto, which we call the Derby game, to study competitive allocation of non-interchangeable resources, such as campaign surrogates in politics or skilled workers in companies, and analyze its Nash equilibria. While Derby games unsurprisingly admit no pure Nash equilibria, our main results surprisingly show that Nash equilibria generically exist where one player plays a pure strategy, and we give necessary and sufficient conditions for such equilibria. Akash Gaonkar, Divya Raghunathan, S. Matthew Weinberg |
EC | 2 |
| 2020 | Switch Code Generation Using Program SynthesisabstractWriting packet-processing programs for programmable switch pipelines is challenging because of their all-or-nothing nature: a program either runs at line rate if it can fit within pipeline resources, or does not run at all. It is the compiler's responsibility to fit programs into pipeline resources. However, switch compilers, which use rewrite rules to generate switch machine code, often reject programs because the rules fail to transform programs into a form that can be mapped to a pipeline's limited resources---even if a mapping actually exists. Michael D. Wong, Divya Raghunathan, Aatish Kishan Varma, Pravein G. Kannan, Anirudh Sivaraman, Srinivas Narayana, Aarti Gupta |
SIGCOMM | 4 |
| 2019 | Knowledge Compilation for Boolean Functional SynthesisabstractGiven a Boolean formula F(X, Y), where X is a vector of outputs and Y is a vector of inputs, the Boolean functional synthesis problem requires us to compute a Skolem function vector Ψ(Y) such that F(Ψ(Y), Y) holds whenever ∃X F(X, Y) holds. In this paper, we investigate the relation between the representation of the specification F(X, Y) and the complexity of synthesis. We introduce a new normal form for Boolean formulas, called SynNNF, that guarantees polynomial-time synthesis and also polynomial-time existential quantification for some order of quantification of variables. We show that several normal forms studied in the knowledge compilation literature are subsumed by SynNNF, although SynNNF can be super-polynomially more succinct than them. Motivated by these results, we propose an algorithm to convert a specification in CNF to SynNNF, with the intent of solving the Boolean functional synthesis problem. Experiments with a prototype implementation show that this approach solves several benchmarks beyond the reach of state-of-the-art tools. S. Akshay 0001, Jatin Arora 0002, Supratik Chakraborty, S. Krishna 0004, Divya Raghunathan, Shetal Shah |
FMCAD | 5 |