In recent years, 3D stacking has emerged as a promising technology for high-performance CPUs, as it offers higher yield and improved inter-die bandwidth. However, 3D CPUs are more vulnerable to thermal problems than conventional 2D CPUs due to increased power density and limited heat dissipation capabilities. In this paper, we analyze the thermal characteristics of off-the-shelf 2D and 3D CPUs, comparing them in terms of performance and on-chip temperature. In addition, to mitigate the thermal vulnerability of 3D CPUs, we introduce two thermal-aware scheduling techniques: 1) floorplan-based thermal-aware scheduling, and 2) adaptive voltage scaling (AVS)-based thermal-aware scheduling. Floorplan-based thermal-aware scheduling primarily assigns tasks to cores that are advantageous for heat dissipation based on the floorplan to mitigate thermal hotspots. AVS-based thermal-aware scheduling prioritizes the allocation of tasks to cores with lower power consumption, considering different power consumption due to process variation. Our evaluation results demonstrate that floorplan-based and AVS-based thermal-aware scheduling reduce energy consumption by 10.3% and 12.4%, respectively, compared to the legacy Linux scheduler, while maintaining performance.

Recent edge devices show high power density in CPUs, resulting in excessive heat generation. Since mechanical cooling solutions are impractical in edge devices due to their small form factor, software-controlled dynamic thermal management (DTM) plays a crucial role in resolving thermal problems. In state-of-the-art edge devices, proactive DTM techniques such as ARM intelligent power allocation (IPA) mainly exploit the current CPU status (e.g., on-chip temperature, core utilization, and frequency) to estimate the current power consumption which eventually affects the future on-chip temperature. However, they overlook the impact of instruction complexity on thermal behaviors, which results in too conservative or aggressive voltage and frequency control. Even with the same frequency and core utilization, the on-chip temperature increases with different gradients depending on the instruction complexity of workloads. In this paper, we propose an instruction complexity aware DTM technique for edge devices, called ComBoost. Based on the real-time monitoring of on-chip temperature, utilization, and frequency, ComBoost examines the instruction complexity as well as the current CPU status to determine the target frequency. ComBoost then proactively adjusts the voltage and frequency of cores to minimize the performance degradation from thermal throttling. In the off-the-shelf edge device, ComBoost improves performance by 16.8%, 18.6%, and 15.5%, on average, compared to the legacy, IPA, and prior RL-based technique, respectively.

Exponential growth in deep neural network (DNN) model size has resulted in significant demands for memory bandwidth, leading to the extensive adoption of high bandwidth memory (HBM) in DNN inference. However, with the shorter retention time due to high operating temperature, HBM requires more frequent refresh operations, suffering larger refresh energy/performance overhead. In this paper, we propose Sparrow ECC, a lightweight but stronger HBM ECC technique for less refresh operations while preserving inference accuracy. Sparrow ECC exploits the dominant exponent pattern (i.e., value similarity) in pre-trained DNN weights, limiting the exponent value range of the pre-trained weights to prevent anomalously large weight value change due to the errors. In addition, through duplication and single error correction (SEC) code, Sparrow ECC strongly protects the critical bits in DNN weights. In our evaluation, when the proportion of 1→0 bit errors is 100% and 99%, Sparrow ECC reduces the refresh energy consumption by 90.40% and 93.22%, on average, respectively, compared to the state-of-the-art (RS(19,17)+ZEM [22]) refresh reduction technique, while preserving inference accuracy.

Virtualized data centers usually consist of heterogeneous servers which have different specifications (performance). Though there are usually a number of unused servers with different performance in such heterogeneous data centers, conventional DVFS (Dynamic Voltage and Frequency Scaling)-based DTM (Dynamic Thermal Management) techniques do not exploit the unused servers to cool down hot servers. In this paper, we propose a novel DTM technique which adaptively exploits external computing resources (unused servers with different performance) as well as internal computing resources (unused CPU cores in the server) available in heterogeneous data centers. When the temperature of a CPU core in a server exceeds a pre-defined thermal threshold, our proposed technique first identifies memory intensiveness and usage of VMs (Virtual Machines). Depending on the memory intensiveness and usage of VMs, our technique adaptively employs the following three methods: 1) a method that migrates a VM to another server with different performance, 2) a method that migrates VMs among CPU cores in the server, and 3) a DVFS-based method. In our experiments, our proposed technique improves performance by 9.6% and saves system-wide EDP by 12.9%, on average (by up to 17.1% and 24.5%, respectively), compared to a conventional DVFS-based DTM technique, satisfying thermal constraints.