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Mohammad Sadegh Sadeghi

dblp:248/4717 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0003-2661-2630ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 50% Reconfigurable computing and FPGAs · 50%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network-on-chip design
network-on-chip security
0.412019
Toward On-chip Network Security Using Runtime Isolation Mapping · ACM Trans. Archit. Code Optim. 2019
Reconfigurable computing and FPGAs › application mapping
runtime application mapping
0.412019
Toward On-chip Network Security Using Runtime Isolation Mapping · ACM Trans. Archit. Code Optim. 2019
Hardware security and side channels › side-channel attack
timing side channel
0.112019
Toward On-chip Network Security Using Runtime Isolation Mapping · ACM Trans. Archit. Code Optim. 2019

Methods — techniques the papers use, named apart from their topics

runtime mapping · 0.8
YearPublicationVenuePosition
2019 Toward On-chip Network Security Using Runtime Isolation Mapping
abstract
Many-cores execute a large number of diverse applications concurrently. Inter-application interference can lead to a security threat as timing channel attack in the on-chip network. A non-interference communication in the shared on-chip network is a dominant necessity for secure many-core platforms to leverage the concepts of the cloud and embedded system-on-chip. The current non-interference techniques are limited to static scheduling and need router modification at micro-architecture level. Mapping of applications can effectively determine the interference among applications in on-chip network. In this work, we explore non-interference approaches through run-time mapping at software and application level. We map the same group of applications in isolated domain(s) to meet non-interference flows. Through run-time mapping, we can maximize utilization of the system without leaking information. The proposed run-time mapping policy requires no router modification in contrast to the best known competing schemes, and the performance degradation is, on average, 16% compared to the state-of-the-art baselines.
Mohammad Sadegh Sadeghi, Siavash Bayat Sarmadi, Shaahin Hessabi
ACM Trans. Archit. Code Optim.1