Spiking Neural Networks (SNN) are quickly gaining traction as a viable alternative to Deep Neural Networks (DNN). In comparison to DNNs, SNNs are more computationally powerful and provide superior en-ergy efficiency. SNNs, while exciting at first appearance, contain security-sensitive assets (e.g., neuron threshold voltage) and vulnerabilities (e.g., sensitivity of classification accuracy to neuron threshold voltage change) that adversaries can exploit. We investigate global fault injection attacks by employing external power supplies and laser-induced local power glitches to corrupt crucial training parameters such as spike amplitude and neuron's membrane threshold potential on SNNs developed using common analog neurons. We also evaluate the impact of power-based attacks on individual SNN layers for 0% (i.e., no attack) to 100% (i.e., whole layer under attack). We investigate the impact of the attacks on digit classification tasks and find that in the worst-case scenario, classification accuracy is reduced by 85.65%. We also propose defenses e.g., a robust current driver design that is immune to power-oriented attacks, improved circuit sizing of neuron components to reduce/recover the adversarial accuracy degradation at the cost of negligible area and 25% power overhead. We also present a dummy neuron-based voltage fault injection detection system with ~ 1% power and area overhead.

In-memory computing (IMC) can eliminate data movement between processor and memory, which is a barrier to the energy efficiency and performance in von Neumann computing. Due to low power consumption, fast operation, and tiny footprint in crossbar architecture, resistive RAM (RRAM) is one of the most promising devices for IMC applications. We present FPCAS, a pipelined floating point (FP) arithmetic (addition/ subtraction) solver based on RRAM crossbars. Although promis- ing, RRAM-based computing may experience random failures, such as the stuck-at fault where RRAM cells are stuck at either a high-resistance state (HRS), i.e., stuck-at-0 (SA0), or a low-resistance state (LRS), i.e., stuck-at-1 (SA1). We propose techniques to prevent SA1 failures, namely, shifting-at-the-output (SATO), force to$V_{\mathrm{ DD}}$(FTV), and force to ground (FTG) since 96% of the RRAMs employed in our architecture are in HRS. Using an extra clock cycle, both strategies employ the memory array’s fault-free RRAMs to conduct the computation. When the failure rate is less than 2%, SATO can manage more than 70% of faults, whereas FTV can handle more than 90% of faults at low power and low area overhead. Simulation results reveal that, for$\mathrm{\scriptstyle NAND}$–$\mathrm{\scriptstyle NAND}$- and$\mathrm{\scriptstyle NOR}$–$\mathrm{\scriptstyle NOR}$-based implementations, FPCAS consumes 335 and 322 pJ, respectively. Both implementations incur a performance overhead of 50% at the array level and 4% for pipelined FP implementation.

Data movement between memory and processing units poses an energy barrier to Von-Neumann-based architectures. In-memory computing (IMC) eliminates this barrier. RRAM-based IMC has been explored for data-intensive applications, such as artilicial neural networks and matrix-vector multiplications that are considered as “soft” tasks where performance is a more important factor than accuracy. In “hard” tasks such as partial differential equations (PDEs), accuracy is a determining factor. In this brief, we propose ReLOPE, a fully RRAM crossbar-based IMC to solve PDEs using the Runge-Kutta numerical method with 97% accuracy. ReLOPE expands the operating range of solution by exploiting shifters to shift input data and output data. ReLOPE range of operation and accuracy can be expanded by using line-grained step sizes by programming other RRAMs on the BL. Compared to software-based PDE solvers, ReLOPE gains 31.4× energy reduction at only 3% accuracy loss.

In-memory computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing. The functions implemented in such in-memory architectures are often proprietary and constitute confidential intellectual property (IP). Our studies indicate that IMC architectures implemented using resistive RAM (RRAM) are susceptible to side channel attack (SCA). Unlike the conventional SCAs that are aimed to leak private keys from cryptographic implementations, SCA on IMC for reverse engineering (SCARE) can reveal the sensitive IP implemented within the memory through power/timing side channels. Therefore, the adversary does not need to perform invasive reverse engineering (RE) to unlock the functionality. We demonstrate SCARE by taking recent IMC architectures, such as dynamic computing in memory (DCIM) and memristor-aided logic (MAGIC) as test cases. Simulation results indicate that AND, OR, and NOR gates (which are the building blocks of complex functions) yield distinct power and timing signatures based on the number of inputs, making them vulnerable to SCA. We show that adversary can use templates (using foundry-calibrated simulations or fabricating known functions in test chips) and analysis to identify the structure of the implemented function by testing a limited number of patterns. We also propose countermeasures, such as redundant inputs and expansion of literals. Redundant inputs can mask the IP with 25% area and 20% power overhead. However, functions can be found at higher RE effort. Expansion of literals incurs 36% power overhead. However, it imposes a brute force search increasing the adversarial RE effort by$3.04\times $.

Autonomous systems e.g., cars and drones generate vast amount of data from sensors that need to be processed in timely fashion to make accurate and safe decisions. Majority of these computations deal with Floating Point (FP) numbers. Conventional Von-Neumann computing paradigm suffers from overheads associated with data transfer. In-memory computing (IMC) can solve this challenge by processing the data locally. However, in-memory FP computing has not been investigated before. We propose F P arithmetic (adder/subtractor and multiplier) using Resistive RAM (ReRAM) crossbar based IMC. A novel shift circuitry is proposed to lower the shift overhead inherently present in the FP arithmetic. The proposed single precision FP adder consumes 335 pJ and 322 pJ for NAND-NAND and NOR-NOR based implementation for addition/subtraction, respectively. The proposed adder/subtractor improves latency, power and energy by 828X, 3.2X, and 3.7X, respectively, compared to MAGIC [1]. Furthermore, the proposed multiplier reduces energy per operation by 1.13X and improves performance by 4.4X compared to ReVAMP [2].

Emerging non-volatile memory (NVM) technologies are being aggressively explored to replace and/or assist conventional CMOS technology. Although NVMs can cut down leakage power, achieve low footprint and allow compute capability along with storage, they suffer from new sources of variability. We review the noise sources associated with NVMs and describe resilience enhancement techniques for both memory and computing. We also present security applications where noise and variability is desirable.

In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ~90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].