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Ching-Jan Chen
dblp:248/5007
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5ranked-venue papers
0as first author
4since 2021 · last 2024
0000-0003-4696-0464ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient ResponseabstractIn this paper, a KY-boost converter with double injection control for the mobile devices is presented. The conventional boost converter suffers from several issues, including large output voltage ripples and slow line and load transient responses. A KY-boost converter is a good candidate to overcome the above drawbacks which has buck-like characteristics. A KY boost converter integrated circuit (IC) is proposed in this paper to achieve better line and load transient responses with the smallest chip size compared with the prior arts. A double injection control is proposed in the KY-boost converter to improve line transient response without affecting loop gain and load transient response. Besides, the issues of start-up and larger chip size for KY converter are improved by the all NMOS power stage design with cross-coupled gate driver. The proposed KY-boost converter IC was fabricated with 0.18-$\mu $m CMOS process, and the overall chip area is 1.1 mm2 including pads. The measured peak efficiency of this work can achieve 92.95%. When the proposed double injection control is enabled, the output voltage deviation during line transition can be reduced by more than 200% from 80 mV to 36 mV compared with input voltage feedforward control. Yu-Ting Hung, Chieh-Ju Tsai, Ching-Jan Chen, Chan-Hsuan Hsu, Chun-Yu Hsieh |
IEEE Trans. Circuits Syst. I Regul. Pap. | 3 |
| 2024 | A 2 μ A Iq Passive-Ramp-Adaptive-Extended-TON Controlled Buck Converter Leveraging Clamped Adaptive Biased Error Amplifier to Achieve DVS/Load Transient One-Cycle Recovery TimeabstractThis paper introduces a low quiescent current buck converter tailored for mobile System-on-Chip (SoC) applications, featuring one-cycle dynamic voltage scaling (DVS) and load transient response, which prior arts cannot achieve simultaneously. A passive ramp adaptive extended-on-time (PSR-AET$_{\mathrm {ON}}$) control scheme ensures efficient operation under varying load conditions, particularly during mobile device gaming and sleeping. The modulation strategy, analyzed via small signal analysis, exhibits a 0 pole in-band characteristic, enabling a simple type-I integrator error amplifier (EA) for regulation. This allows the quiescent current of EA to be scalable with its compensation capacitor. A dynamic-biased EA is further proposed to enhance DVS tracking speed with the 1/3 response time of conventional EA. Additionally, the extended-TON and clamping mechanism address output saturation of the EA reduced the output voltage drop to 1/4 and enables seamless transitions from continuous conduction mode (CCM) to discontinuous conduction mode (DCM). Fabricated using a TSMC$0.18~\mu $m CMOS process, the chip operates at a 4 MHz switching frequency in CCM, exhibits a$2~\mu $A quiescent current, and achieves >85% efficiency across 30000 times load current difference ($40~\mu $A to 1.2A). It demonstrates a$2.8~\mu $s DVS settling time. It showcases an 80 mV undershoot voltage and$1.96~\mu $s recovery time for a 1.8 A/200 ns current step in load transient response, seamlessly transitioning between CCM and DCM within a 24 mV deviation. Chieh-Ju Tsai, Hsiao-Hsuan Chen, Ching-Jan Chen |
IEEE Trans. Circuits Syst. I Regul. Pap. | 3 |
| 2024 | A Phase Interpolated Dual-Phase Adaptive On-Time Controlled Buck ConverterabstractThis paper introduces a dual-phase buck converter that utilizes a phase interpolator for interleaving, based on adaptive on-time control. This method successfully resolves ripple cancellation challenges in multi-phase adaptive on-time controlled buck converters, thereby eliminating the reliance on external ramp signals or complex phase-locked loops. Consequently, the loop bandwidth is expanded, enhancing the converter’s noise immunity and reducing jitter within a compact circuit design. Operating at 3 MHz per phase, the converter demonstrates a maximum jitter of 30.25 ns and a phase error of 7.3 degrees at the ripple cancellation point. Moreover, features like rapid transient on-time extension and a dual-phase full turn-on mechanism significantly improve dynamic performance during load transitions. Experimental results show a voltage drop of 80 mV and a settling time of$2~\mu $s under a 3 A load step, with input and output voltages of 1.8 V and 0.9 V, respectively. Fabricated using the TSMC$0.18~\mu $m CMOS process, the prototype boasts a compact total area of 1.41 mm2, including a 0.03 mm2 phase-interpolator section, achieving a peak efficiency of 95.58%. Chieh-Ju Tsai, Hsiao-Hsuan Chen, Ching-Jan Chen |
IEEE Trans. Circuits Syst. I Regul. Pap. | 3 |
| 2023 | Circulating Current Control (CCC) of Grid-Connected Hybrid Modular Multilevel Converter (MMC) for Solid State Transformer (SST) ApplicationabstractFor convenient interconnection with ac/dc grid, Solid State Transformer (SST) is the more preferable solution according to the current literature. Also, recent advancements in the configuration of Modular Multilevel Converter (MMC) shows how the Hybrid MMCs provide superior performance compared to the conventional half-bridge sub-module (HB-SM) MMC. The Hybrid MMC considered here makes the use of HB SMs in addition to Full-bridge (FB) SMs. For secure operation of MMC, the foremost control objectives need to be fulfilled viz., SM capacitor voltage control, circulating current control, output current control. Thus, the article mainly focuses on this primary control objectives for the grid connected Hybrid MMC, which will be acting as back-end converter of the SST. To balance the SM capacitor voltages of MMC, the reduced switching frequency (RSF) voltage balancing (VB) technique is used in this article. The impact of this technique is compared with the traditional VB method. Then based on double line frequency, dq-frame, the closed loop circulating current control is achieved to eliminate the second harmonic components in the arm currents. Closed loop output current control having the same logic as applicable to three-phase VSC is also implemented. Furthermore, open loop power flow control is used for generating the reference for closed loop current control. To evaluate the performance of the controller, a comparative analysis of Hybrid MMC with and without application of controllers, is executed using MATLAB simulation. The impact of RSF - VB and current controllers is also presented. Akshaya Dinesh Bonde, Pradyumn Chaturvedi, Vijay B. Borghate, Ching-Jan Chen |
IECON | 4 |
| 2012 | A novel constant on-time current-mode control scheme to achieve adaptive voltage positioning for DC power convertersabstractA constant on-time current-mode (COTCM) control features inherent phase-current balancing, good stability margin and improved light-load efficiency which is a new mandate for many CPU power applications nowadays. For a delicate application such as adaptive voltage positioning (AVP) application, however, the output voltage regulation of a COTCM converter is often inadequate when constant converter output impedance feature is also required. In this paper, a modified converter with a DC-offset correction circuit is presented. A small-signal model is also developed based on describing-function approach which is complicated but necessary to uncover the inherent nature of this control scheme. Experimental results will be shown. A comparison with a ripple-based constant on-time (RBCOT) control scheme will also be given. Yung-Jen Chen, Ching-Jan Chen, Chien-Hui Wang |
IECON | 4 |