This paper presents microarchitectural and physical design trade-offs as well as primitive mapping techniques for designing high-throughput area-efficient RISC-V soft-cores. These techniques facilitate the implementation of tiny, highly efficient RISC-V cores that can be scaled to thousands of instances on large FPGAs, enabling massively parallel overlays by pushing above$\mathbf{1. 5}$MIPS/LUT in a single-core setup and over$\mathbf{0. 8 1}$MIPS/LUT in a kilo-core configuration delivering$\mathbf{5 1 2, 0 0 0}$MIPS peak throughput. The proposed fully open-source architecture is analyzed in detail, with a focus on optimizing trade-offs between core pipeline depth, multithreading, clock speed, and configurable parameters, such as the use of Digital Signal Processing (DSP) blocks in the Arithmetic Logic Unit (ALU). The interplay between these parameters is carefully examined to demonstrate their impact on system scalability and throughput. A case study is presented to illustrate the implementation of a kilo-core system, showing how thousands of RISC-V cores can be deployed on a large FPGA platform while maintaining per-core efficiency. This work paves the way for scalable many-core designs on FPGAs (and overlays in general), as they can achieve both a compact area footprint, low power dissipation, and high operating clock speed.

SPARKLE (Scalable Parallel Architecture for RISC-V Kernel-Level Execution) is a RISC-V many-core architecture for scalable parallel software processing, currently running at 400MHz on a Xilinx VU9P FPGA, including a PCIe backplane, with 1,024 cores and 16,384 hardware threads. SPARKLE is highly flexible, allowing various configurations. Its core, BRISKI (Barrel RISC- V for Kilo-core Implementations), operates at 650+ MHz in standalone mode and is one of the fastest barrel processor softcores, supporting full user-mode RV32I and additional instructions such as LRISC atomic instructions and CSRRS for hart ID retrieval.

The overlay architecture enables to raise the abstraction level of hardware design and enhances hardware-accelerated applications’ portability. In FPGAs, there is a growing awareness of the overlay structure as typified by many-core architecture. It works in theory; however, it is difficult in practice, because it is beset with serious design issues. For example, the size of FPGAs is bigger than before. It is exacerbating the issue of the place-and-route. Besides, a single FPGA is actually the sum of small-to-middle FPGAs by advancing packaging technology like silicon interposers. Thus, the tightly coupled many-core designs will face this covert issue that the wires among the regions are extremely restricted. This article proposes efficient essential processing elements, micro-architecture design, and the interconnect architecture toward a scalable many-core overlay design. In particular, our work proposes a novel compact buffering technique to reduce memory resource utilization in tightly connected overlays while preserving computational efficiency. This technique reduces the utilization of BlockRAM to nearly 50% while achieving a best-case computational efficiency of 91.93% in a three-dimensional Jacobi benchmark. Besides, the proposed enhancements led to around 2× and 3× improvement in performance and power efficiency, respectively. Moreover, the improved scalability allowed increasing compute resources and delivering around 4× better performance and power efficiency, as compared to the baseline Dynamically Re-programmable Architecture of Gather-scatter Overlay Nodes overlay.

General-purpose processors offer the best programming flexibility to address a wide range of problems. Nonetheless, they still lack behind special-purpose processors when it comes to sustained computational performance. Here, we leverage the best from both worlds and we propose a flexible, highly scalable, high-performance computing architecture with versatility in mind. The proposed architecture code-named DRAGON, benefits from several forms of parallelism such as SIMD, VLIW, Memory Broadcasting and even vector processing.

Big data, Artificial Intelligence, and cloud services are emerging technologies whose power consumption due to the tremendous amount of computing resources became a significant issue in data centers. FPGA (Field Programmable Gate Array) based accelerators may offer a convenient solution for high-performance and energy-efficient computing. However, designing these accelerators using hardware description language is a burdensome task and requires specialized skill sets. To help not only FPGA engineers but also software programmers to implement their applications quickly, an overlay architecture on an FPGA will be a good candidate. Thus, this paper proposes a coarse-grained overlay architecture with SIMD (Single Instruction Multiple Data) instructions.