The dual-rank configuration is one of the parallelization methods to increase the memory capacity for mobile applications. However, the stub mainly composed of the redistribution layer causes resonance reflections and its reflection interval reaches the bit period, which distorts signal and limits the signal bandwidth. A single-ended duobinary transmitter that utilizes the reflection is presented for dual-rank mobile memory interfaces where reflections dominate. The reflection is included in the transfer function for duobinary modulation, which allows the transmitter to have a wide eye opening and high energy efficiency. Two-tap reverse feed-forward equalization and slew-rate control are used to support the duobinary modulation in combination with the reflection. A prototype chip fabricated in a 65 nm CMOS process has an area of 0.0378 mm2and consumes 1.24 pJ/bit. It is verified at data rates of 8, 9 and 10 Gb/s/pin where the flight time of the 9 mm stub is 55.6 ps.

In this paper, a quadrature signal corrector (QSC) with high accuracy and fast correction for memory interfaces is presented. An adaptive delay gain controller in the QSC adjusts each delay gain of four digitally controlled delay lines (DCDLs) separately depending on skew between the quadrature clocks, resulting in short correction time together with low residual skew. To validate the effectiveness of our QSC in memory interfaces, a quarter-rate single-ended 1-tap decision feedback equalizer (DFE) with the QSC was fabricated in a 65nm CMOS process. Using the adaptive delay gain controller, the QSC reduced the skew between the 3 GHz quadrature clocks from a maximum of 21.2 ps to 0.8 ps while correction time was reduced by a factor of 3.9 compared to that without using the adaptive delay gain controller. At 12 Gb/s, the DFE using our QSC achieved a BER of 10-12with an eye width of 140 mUI when the input clock skew is 13.2 ps.

The increasing data rate of serial links makes it difficult to match timing constraints of serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the timing between data and clock. However, these buffers consume significant power and become sources of noise to the transmitter output. The problem is more serious for serializers other than 2n:1, and using only 2n:1 serializer could be a limitation on system design. In this paper, a 20:1 serializer using two calibration feedback loops is presented to solve this issue and reduce power consumption. The two loops detect the phase difference between data and clock, and automatically align the clock phase to the center of the data phase. The loops eliminate the power-consuming clock buffers on the critical clock path and operate at maximum quarter rate, enabling the transmitter to have low power consumption and high performance. A 6.4 Gb/s serializer prototype is fabricated in 55-nm CMOS process with a 1.2 V supply voltage. It achieves 97.5 ps eye width, which is 62.4% of a unit interval (UI) using PRBS-7 data, and its energy efficiency is 1.60 pJ/bit.