Demo Data from EDBT 2026 / reviewers in the wild / expert
Premkumar Vincent
dblp:249/2224
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0002-5002-3978ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 1 heaviest of 1, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design technology co-optimization |
0.8 | 1 | 2024 | Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
ranking algorithm · 0.8neural tangent kernel · 0.8neural compact model · 0.8active learning · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device ModelingabstractDesign-Technology Co-Optimization (DTCO) can be significantly accelerated by employing Neural Compact Models (NCMs). However, the effective deployment of NCMs requires a substantial amount of training data for accurate device modeling. This paper introduces an Active Learning (AL) framework designed to enhance the efficiency of both device modeling and process optimization, particularly addressing the challenges of time-intensive Technology Computer-Aided Design (TCAD) simulations. The framework employs a ranking algorithm that assesses metrics such as the expected variance from the neural tangent kernel (NTK), TCAD simulation time, and the complexity of I-V curves. This strategy considerably reduces the number of required simulations while maintaining high accuracy. Demonstrating the effectiveness of our AL framework, we achieved a 28.5% improvement in MSE within a 30-minute time budget for device modeling, and an 86.7% reduction in the data points required for process optimization of a 51-stage ring oscillator (RO). These results offer a streamlined, adaptable solution for rapid device modeling and process optimization in various DTCO applications. Chanwoo Park, Premkumar Vincent, Hyunbo Cho |
DAC | 3 |