The increasing deployment of artificial intelligence (AI) at the edge, particularly convolutional neural networks (CNNs) in resource-constrained devices, has created new challenges for ensuring system reliability and safety. Market analysts project a 21% annual growth rate in the edge AI market size over the next five years. These devices are being used in safety-critical applications such as autonomous vehicles, industrial control systems, and medical devices, where malfunctions due to radiationinduced soft errors can have severe consequences, ranging from degraded performance to life-threatening situations. Soft errors, caused by energetic particles, can corrupt data and instructions, resulting in unpredictable system behaviour. To meet safety standards in these domains, reliability engineers must proactively explore and implement efficient mitigation solutions during the initial design cycle.

Security and reliability problems in edge devices can become the Achilles’ heel for their massive use in Internet of Things (IoT) systems. While most works address security by implementing lightweight cryptographic algorithms, this paper is the first to assess the soft error reliability of lightweight cryptographic algorithms targeting IoT edge devices. This paper performs soft error analysis for ten lightweight cryptographic algorithms considering two compilers and running on top of an IoT-ready commercial processor model (i.e. Arm Cortex-M7). From the ten lightweight cryptographic algorithms, IDEA shows the best trade-off between reliability and number of instructions. Index Terms-Lightweight Cryptographic (LWC) Algorithms, Soft Error, Reliability, Internet of Things (IoT), Edge Devices.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety-critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors during the initial design cycle.

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety–critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors at the initial design cycle. This paper presents SOFIA, a framework that integrates: (i) a set of fault injection techniques that enable bespoke inspections, (ii) machine learning methods to correlate soft error results and system architecture parameters, and (iii) mitigation techniques, including: full and partial triple modular redundancy (TMR) as well as a register allocation technique (RAT), which allocates the critical code (e.g., application’s function, machine learning layer) to a pool of specific processor registers. The proposed framework and novel variations of the RAT are validated through more than 1739k fault injections considering a real Linux kernel, benchmarks from different domains and a multi-core Arm processor.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers. Both the critical function and the register pool are automatically selected by a developed profiling tool. The proposed technique was validated through more than 320K fault injections considering a Linux kernel, different benchmarks and two multicore ARM processors. Results show that our technique significantly reduces the code size and performance overheads while providing reliability improvement, w.r.t. the Triple Modular Redundancy (TMR) technique.