Professional success in STEM fields extends beyond technical expertise, requiring strong communication and teamwork skills. While program accreditation agencies emphasize these competencies, traditional classroom methods focus heavily on individual learning, offering limited collaboration opportunities. Digital learning platforms enhance engagement but often lack real-time peer interaction and teamwork. In this work, we present PeerCollate - a scalable, technology-enhanced learning strategy to promote active learning and peer collaboration in STEM curricula within both traditional and hybrid instruction modalities. PeerCollate integrates open-source electronic collaboration tools with Learning Management Systems (LMS) to facilitate structured teamwork, enabling students to engage in problem-solving activities through virtual team-based learning. For instructors, this approach supports dynamic assessment and real-time feedback, improving student engagement and learning outcomes. Additionally, a digitally mediated post-examination remediation method is introduced, where students are grouped based on differing knowledge gaps to encourage peer-assisted learning. Through this collaborative approach, students refine their understanding before meeting with teaching assistants for further clarification and potential opportunity for score adjustments. By fostering teamwork, enhancing problem-solving abilities, and streamlining assessment, this model significantly improves the effectiveness and scalability of STEM education.

Neural networks offer viable alternatives for energy versus accuracy tradeoffs, in particular with regards to the precision of the computational circuit. This paper explores use of progressive modular redundancy of intrinsically low energy, low precision circuits as an alternative to more complex networks yielding higher accuracy directly. Results indicate that a lower footprint temporal modular redundancy, which is applied progressively as needed, can have lower footprint and reduced energy consumption at comparable or slightly reduced accuracy as more complex neural networks. This provides an alternative to binarization and other model compression options for intelligence at the edge of the network. Our Progressive Modular Redundancy approach using varied activations implemented using a$\mathbf{784}\times \mathbf{100}\times \mathbf{10}$network shows a 3% improvement in accuracy compared to the baseline case of$\mathbf{784}\times \mathbf{500}\times \mathbf{500}\times \mathbf{10}$network with sigmoidal activation, at 86.1% and 87% reduction in power and weighted crossbar normalized area overhead, respectively, 87.5% reduction in power error product (PEP) at the cost of ~2.6x increased throughput latency.

Compressive sensing (CS) is a promising technique for transmitting signals in power-critical applications such as Internet of Things (IoT) devices. Nonuniform CS optimizes this process by adjusting sampling frequency based on the relative importance levels characterized by the signal of interest. Recent advances have yielded energy-efficient hardware implementations of CS sampling, leveraging spin-based crossbar architectures for in-memory vector-matrix multiplication and through the use of probabilistic bit (p-bit) devices to generate tunable random outputs for writing the array. Thus, a region of interest is generated via column-ordered density of on-state devices. Herein, we propose a simple design for supplying inputs to the p-bit devices, based on Ohmic voltage attenuation occurring along the word lines of the crossbar array. The technique embeds some required computations to be conducted intrinsically by the cross-points of the memristive array, thus bypassing overheads of conventional instruction execution and eliminating the need for costly hardware components, such as lookup tables (LUTs) and data converters. The design is shown to be robust for various array sizes and parasitics while generating the appropriate tuning signals within a single clock cycle duration of 1.6 ns, and at an energy overhead of 333 fJ. Compared with a standard approach using LUTs and digital to-analog converters, the design herein achieves a 583-fold reduction in energy and 23-fold reduction in transistor count.