The rapid advancement of photonic integrated circuits is driving innovations in interconnect, computing, and sensing applications. This progress has led to the development of nanophotonic waveguide devices with complex geometries, offering greater design flexibility and a wider range of functional applications. However, electromagnetic (EM) simulation imposes a heavy computational burden during the design and validation phases. This significantly hampers design iteration speed and scalability. Although existing data-driven methods and physics-informed neural networks have shown promise for simpler structures, they fall short for highly complex geometries, limiting the automation of photonic device design. To address these issues, we present the SuperPhys-Net framework. This innovative approach enhances coarse-grid simulation results through super-resolution and integrates physical constraints to generate fine-grid solutions that adhere to physical laws. Our model demonstrates outstanding performance across complex nanophotonic waveguide devices with varying dimensions, achieving a 72.61% improvement in accuracy over current state-of-the-art models. Additionally, it reduces computational time by 76.09% compared to standard finite-difference frequency-domain solvers, all while maintaining exceptional accuracy across all scales.

Photonic integrated circuits (PICs) design has been challenged by the complex physics behind various integrated photonic devices. Inverse design offers an effective design automation solution for obtaining high-performance and compact pho-tonic devices using computational algorithms and electromagnetic (EM) simulations. However, the challenge lies in transforming the fabrication-infeasible device geometries obtained from computational algorithms into reliable while optimal physical design. In-corporating fabrication constraints into the optimization iterations can extend running time and lead to performance compromise. In this work, we proposed a novel DRC-aware photonic inverse design framework, leveraging the bi-level optimization to enable end-to-end gradient-based device optimization. Our method can guarantee all intermediate devices on the optimization trajectory adhere to fabrication requirements and rules. The proposed workflow eliminates the need for a binarization process and fabrication constraint adaption, thus enabling a fast and efficient search for high-performance and reliable integrated photonic devices. Experimental results demonstrate the benefits of our proposed method, including improved device performance and reduced EM simulations and running time.

Optical interconnects have emerged as a promising solution for rack-, board-scale, and even in-package communications, thanks to their high available optical bandwidth and minimal latency. However, the optical waveguides are intrinsically different from traditional metal wires, especially the phase matching constraints, which impose new challenges for routing in the photonic in-tegrated circuits design. In this paper, we propose a comprehensive and efficient optical routing framework that introduces a diffuse-based length-matching method and bend modification methods to ensure phase-matching constraints. Furthermore, we present a congestion-based A * formulation with a negotiated congestion-based rip-up and reroute strategy on new rectangular grids with an aspect ratio of 1:$\sqrt{3}$to reduce insertion loss. Experimental results based on real photonic integrated designs show that our optical routing flow can reduce total insertion loss by 11 % and maximum insertion loss by 108 %, while effectively satisfying matching constraints, compared to manual results.

While large language models (LLMs) have shown remarkable potential in automating various tasks in digital chip design, the field of Photonic Integrated Circuits (PICs)-a promising solution to advanced chip designs-remains relatively unexplored in this context. The design of PICs is time-consuming and prone to errors due to the extensive and repetitive nature of code involved in photonic chip design. In this paper, we introduce PICBench, the first benchmarking and evaluation framework specifically designed to automate PIC design generation using LLMs, where the generated output takes the form of a netlist. Our benchmark consists of dozens of meticulously crafted PIC design problems, spanning from fundamental device designs to more complex circuit-level designs. It automatically evaluates both the syntax and functionality of generated PIC designs by comparing simulation outputs with expert-written solutions, leveraging an open-source simulator. We evaluate a range of existing LLMs, while also conducting comparative tests on various prompt engineering techniques to enhance LLM performance in automated PIC design. The results reveal the challenges and potential of LLMs in the PIC design domain, offering insights into the key areas that require further research and development to optimize automation in this field. Our benchmark and evaluation code is available at https://github.com/PICDA/PICBench.

As silicon photonic integrated circuits (PICs) scale in density and integration level, thermal crosstalk significantly impacts chip performance and reliability, necessitating careful thermal-aware design. Traditional numerical solvers are prohibitively slow for large-scale 3D simulation, while existing machine learning surrogates struggle with generalization, especially under the complex distributed heaters and layered structures unique to PICs. We present ThermoPhoton, an operator-learning neural architecture tailored for efficient, accurate 3D thermal modeling of PICs. ThermoPhoton introduces a Pseudo-3D source representation (Pseudo-3D) that leverages device stratification, and applies Zero Coordinate Shift (ZCS) encoding to optimize physics-informed loss computation. Attention mechanisms further enhance the capture of sharp thermal gradients and crosstalk. On industry-standard benchmarks, ThermoPhoton achieves a mean absolute percentage error of 0.07%, reduces peak GPU memory by 67.1%, and shortens training time by 37.9% compared to prior operator-based methods, enabling fast, reliable, and scalable thermal analysis for next-generation photonic chips.

Photonic integrated circuits (PICs) have emerged as a promising solution for next-generation computing and interconnects, delivering enhanced performance in bandwidth and energy efficiency compared to conventional electronics. Previous studies on automatic optical routing have typically assumed uniform waveguide classes, neglecting the real-world requirement for multiple waveguide types to enhance performance and integration density. To address this gap, we propose an adaptive waveguide routing framework explicitly tailored for PICs that effectively handles hybrid waveguide classes. Our method starts with a fast initial routing algorithm that optimizes waveguide paths, considering target net lengths or length matching constraints among nets, minimizing bends, and ensuring compatibility with hybrid waveguide usage. We further enhance routing quality using a mixed integer linear programming (MILP)-based automatic transition insertion technique, strategically employing different waveguide types to significantly reduce transmission loss and ensure compliance with stringent matching constraints. Experimental results show that, compared to prior approaches, our algorithm reduces total insertion loss by up to 37% on average in target-length routing scenarios, and achieves an average reduction of 5% in total insertion loss and 14% in maximum loss in multi-net cases while satisfying all constraints.