Demo Data from EDBT 2026 / reviewers in the wild / expert
Ramune Nagisetty
dblp:249/3803
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Hardware accelerators and domain-specific architectures · 38% Integrated circuit design · 12% |
Topics — the 2 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
packaging |
0.1 | 1 | 2021 | Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems · DAC 2021 |
Electronic design automation
physical design |
0.1 | 1 | 2021 | Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems · DAC 2021 |
Methods — techniques the papers use, named apart from their topics
machine learning · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Convergence of SoC architecture and semiconductor manufacturing through AI/ML systemsabstractAI/ML systems have been deployed in both SoC design/architecture as well as in semiconductor manufacturing over the years. These systems have been independent of each other with process design kits (PDK) being the interface between design and manufacturing. Recent advances in packaging technology and the adoption of chiplet architecture has opened exciting avenues for merged AI/ML systems that bring SoC architecture and manufacturing together. This work explores this opportunity of enabling an AI/ML system that brings manufacturing and design information together for chiplet architecture exploration Srinivas Bodapati, Pushkar Ranade, Ramune Nagisetty |
DAC | 3 |