Self-timed and pulse mode circuit modules are often implemented using combinational logic with feedback, or require timing constraints for the circuit to function correctly. Identifying causal paths through these circuit modules is a fundamental requirement to enable automatic system level timing closure, performance analysis, and timing-driven optimizations when using static timing analysis algorithms. A methodology and algorithm for identifying causal paths in cyclic sequential circuits under arbitrary timing models are presented. The algorithm identifies causal paths in a sequential circuit implemented with standard cell gates. The algorithm is demonstrated by identifying causal paths for over 100 asynchronous finite-state machines and timed circuits designed using a variety of timing models. Cyclic paths, pulse generating paths, and unbounded length self-enabling loops are identified inside these circuit blocks. Some of the causal paths in these designs have never been previously identified. No preliminary versions of this work have been previously published.