Augusto Andre Souza Berndt

dblp:249/8820 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2023
—ORCID · none

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Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2023 Adaptive Batch Size CGP: Improving Accuracy and Runtime for CGP Logic Optimization Flow
Bryan Martins Lima, Naiara Sachetti, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho
EuroGP3
2022 Optimizing machine learning logic circuits with constant signal propagation
Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen
Integr.1
2021 Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
abstract
Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita 0004, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong Roland Jiang, Jiaqi Gu 0002, Zheng Zhao 0003, Zixuan Jiang, David Z. Pan, Brunno Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar 0001, Wei Zeng 0015, Azadeh Davoodi, Rasit Onur Topaloglu, Jordan Dotzel, Yichi Zhang 0006, Hanyu Wang 0005, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
DATE23
2021 Fast Logic Optimization Using Decision Trees
abstract
This work evaluates the use of Decision Trees (DTs) methods for a fast logic minimization of Boolean functions. The proposed DT approach is compared to traditional Espresso logic minimizer and the minimization algorithms available in the ABC tool. The methods are compared with respect to the execution time, number of nodes and number of logic levels. The DT methods proved to be a faster alternative, reducing time by an average of 52% and 5.5% when compared to Espresso and ABC respectively, while keeping competitive results in terms of AIG depth and number of nodes. Additionally, in order to obtain smaller circuits at the cost of approximate results we tested DTs with limited tree depth. The trade-offs between synthesis time, circuit area and accuracy are also discussed. Compared to ABC, limiting the maximum tree depth leads to time savings of up to 52%, up to 86% less number of nodes, and up to 48% lower AIG depth, while maintaining acceptable accuracy results.
Brunno Abreu, Augusto Andre Souza Berndt, Isac de Souza Campos, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi
ISCAS2