A static timing verifier is an important tool in the design of a complex high performance VLSI chip such as an Alpha CPU. A timing verifier uses a simple and pessimistic delay model to identify critical failing paths in the design, which then need to be fixed. However, the pessimistic delay model results in a large number of correct paths being identified as failing paths, possibly leading to wasted design resources. Therefore, each critical path identified by the timing verifier needs to be analyzed using a circuit simulator such as SPICE in order to confirm that it is a real failure. Setting up such a simulation is complex, especially when the critical path consists of structures appearing in a datapath of the CPU. In this paper, we present algorithms for the construction of a model for simulating the maximum delay through a critical path. This technique has been used to analyze several critical paths during the design of a 300 MHz Alpha CPU.

The design and verification of the NVAX microprocessor are described. Full-custom circuit and layout techniques were required to achieve the target cycle time, and the design had to be completed as quickly as possible to meet time-to-market requirements. A structured design methodology and several novel proprietary CAD tools were used to develop the full custom chip from a textual specification to tape out in 20 months. First silicon booted the VMS operating system, worked in symmetric multiprocessing system configurations, and operated at 83.3 MHz under worst-case operating conditions.>

Static timing verification on a large full-custom design isan extremely challenging problem for which no complete solution exists.In this paper, we present our experience on the timing verification of our next generation CMOS CPU design using an internally developed tool, NTV.The entire chip, which consists of 1.2M transistors and 500K nodes, has been verified by NTV in less than 7 CPU hours on a VAX-8800.42K timing constraints were verified and 350K signal paths were traced.Among the reported critical paths, 85% were already known to designers and the remaining 15'%0were unforeseen critical paths.

A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV.>

Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.>

The Meyer capacitance model (see RCA Rev., vol.32, p.42-63, 1971) fails to obey the charge conservation law. It is shown that the charge nonconservation in the Meyer model is not due to any physical assumptions. Rather, it is caused by the mathematical error of characterizing a multidimensional function (the stored charge on the four terminals of a MOSFET) by an incomplete subset of its partial derivatives (the partial derivatives of the gate charge). This conclusion is supported by developing and implementing a correct mathematical characterization of the MOS charges based on the same physical assumptions used in the Meyer model. One important outcome of this exercise is that the nonreciprocal nature of MOS capacitive coupling is evident even in a first-order physical model of the device.>