While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).>

The Astronautics ZS-1 is a high speed minisupercomputer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture which splits instruction words into two streams, one for fixed-point/memory-address computation and the other for floating-point operations. The two instruction streams are then processed in parallel, with architectural queues providing communication between the streams. Pipelining is used extensively throughout the ZS-1. The combination of decoupling and pipelining provides overall, sustained performance of about one third a CRAY-XMP-1 on compiled double-precision Fortran. The authors give a description of the decoupled architecture and discuss other forms of parallelism used in the ZS-1. A discussion of static and dynamic instruction scheduling is also included.>

The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. Descriptions of the instruction set, pipeline structure, and virtual memory implementation demonstrate the methods used to satisfy the objectives. High performance is achieved through a combination of static (compile-time) instruction scheduling and dynamic (run-time) scheduling. Both types of scheduling are illustrated with examples.