This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each of the coprocessors of Crypto-Tile is dedicated to a specific family of cryptographic algorithms, offering functions for symmetric and public-key cryptography, computation of digests, generation of random numbers, and Post-Quantum cryptography. The performances of each coprocessor outperform other available solutions, offering innovative hardware-native services, such as key management, clock randomisation and access privilege mechanisms. The system has been synthesised on a 7 nm standard-cell technology, being the first Cryptoprocessor to be characterised in such an advanced silicon technology. The post-synthesis netlist has been employed to assess the resistance of Crypto-Tile to power analysis side-channel attacks. Finally, a demoboard has been implemented, integrating a RISC-V softcore processor and the Crypto-Tile module, and drivers for hardware abstraction layer, bare-metal applications and drivers for Linux kernel in C language have been developed. Finally, we exploited them to compare in terms of execution speed the hardware-accelerated algorithms against software-only solutions.

Artificial intelligence (AI) is becoming increasingly relevant for space applications, reducing reliance on high-bandwidth downlinks. Its use, however, has primarily been demonstrated in low Earth orbit (LEO) using commercial off-the-shelf (COTS) components. Extending its use to deep-space and long-duration missions requires computing platforms capable of operating in harsh radiation environments without incurring prohibitive costs. This is particularly important for systems implemented on field-programmable gate arrays (FPGAs), which are widely used in space applications due to their scalability and support for various radiation-hardening profiles. This flexibility makes them preferable to application-specific integrated circuits, whose low production volumes often do not justify their use in space systems. This article details our efforts to develop a novel system-on-chip (SoC) featuring GPU@SAT, a soft graphic processing unit IP provided by IngeniArs S.r.l., with a focus on enhancing its robustness when implemented on the Xilinx radiation-tolerant XQRKU060 FPGA. This approach leverages FPGA reconfigurability and radiation tolerance alongside the high-performance capabilities of graphic processing units (GPUs), unlocking significant potential for accelerating compute-intensive tasks in edge-space applications. Building on this foundation, we employ a classification-based methodology to improve the fault tolerance of GPU@SAT, analyzing trade-offs on performance, power, and area. Additional IP cores, such as a watchdog timer (WDT), a dual RISC-V lockstep with rollback, and the Xilinx Soft Error Mitigation IP, are employed to further improve the SoC robustness. Fault injection on an FPGA prototype targeting essential configuration bits validates the approach, showing a$15.4\times $improvement in mean injections before failure over the baseline architecture, with only a$1.2\times $increase in hardware complexity.

The rapid development of Artificial Intelligence (AI) algorithms has created a need for a resource-optimised hardware accelerator. Among various platforms, Coarse-Grained Reconfigurable Array (CGRA) have gained importance as on-edge accelerators. They comprise of heterogeneous Processing Element (PE) matrix, which allows for high flexibility and parallelisation of calculations. They are mainly used for speeding up Data Flow Graph (DFG) execution. We aim to provide a general purpose, highly parameterised, and flexible architecture for AI on-edge data crunching. We propose a CGRA with a vector extension which allows for dynamically adjustable precision of calculation while maintaining a desired performance-power-area optimisation. It targets 4 bits integer (INT4) and 8 bits integer (INT8) quantization for fast and efficient Neural Network (NN) processing. In this paper, we examined hardware costs required to support the vector extension functionality. We synthesised the design on the 40nm Standard-Cell technology from TSMC. The obtained results show that the proposed extension attains on average 28.2% decrease in power consumption and 21.6% decrease in area compared to a reference design of the same computation power.

Modern computing platforms exploiting Coarse-Grained Reconfigurable Array architectures depend highly on the efficiency with which data are handled inside the architecture. Moving data is critical in computing-intensive systems to maximize energy efficiency and reduce latency. Access to the main memory is the most costly operation; therefore, the data retrieved must be kept near the processing elements of the architecture as long as possible to reduce data transfers. Modern algorithms involve very different access patterns to the main memory, requiring high versatility for Direct Memory Access (DMA) mechanisms. This work presents the SmartDMA architecture, a RISC-V-based programmable DMA controller specifically designed to perform adaptable memory access patterns and implement proper data reuse policies in CGRA-based systems. It comprises a set of Data Mover Engines (DMEs) that implement configurable 1D, 2D, and 3D data movements. Using a custom RISC-VISA extension and a programmable event network, the application-specific firmware loaded on the SmartDMA can schedule DMA commands among all DMEs, ensuring that they are always busy with data transactions. We show a typical use case that takes advantage of CGRA-based processing and highlights the functionality of the SmartDMA. We synthesized the SmartDMA on TSMC 40nm low-power standard-cell technology at 350 MHz for three architectural configurations, increasing the number of DMEs, with a maximum memory throughput of 5.6 GB/s: small, medium, and large. The small configuration occupies 46.2k um2 of cell area and consumes 8.64 mW. The medium occupies 117k um2 and consumes 23.1 mW. The large one occupies 243k um2 and consumes 42.7 mW.

Artificial intelligence (AI) is paving the way for a new era of algorithms focusing directly on the information contained in the data, autonomously extracting relevant features for a given application. While the initial paradigm was to have these applications run by a server hosted processor, recent advances in microelectronics provide hardware accelerators with an efficient ratio between computation and energy consumption, enabling the implementation of AI algorithms “at the edge.” In this way only the meaningful and useful data are transmitted to the end-user, minimizing the required data bandwidth, and reducing the latency with respect to the cloud computing model. In recent years, European Space Agency (ESA) is promoting the development of disruptive innovative technologies on-board earth observation (EO) missions. In this field, the most advanced experiment to date is the$\Phi $-sat-1, which has demonstrated the potential of artificial intelligence (AI) as a reliable and accurate tool for cloud detection on-board a hyperspectral imaging mission. The activities involved included demonstrating the robustness of the Intel Movidius Myriad 2 hardware accelerator against ionizing radiation, developing a Cloudscout segmentation neural network (NN), run on Myriad 2, to identify, classify, and eventually discard on-board the cloudy images, and assessing the innovative Hyperscout-2 hyperspectral sensor. This mission represents the first official attempt to successfully run an AI deep convolutional NN (CNN) directly inferencing on a dedicated accelerator on-board a satellite, opening the way for a new era of discovery and commercial applications driven by the deployment of on-board AI.

This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encryption standard (AES)-based block cipher modes, including the more advanced cipher-based MAC (CMAC), counter with CBC-MAC (CCM), Galois counter mode (GCM), and XOR-encrypt-XOR-based tweaked-codebook mode with ciphertext stealing (XTS) modes. The proposed design implements advanced and innovative features in HW, such as AES key secure management, on-chip clock randomization, and access privilege mechanisms. The system has been tested in a RISC-V-based system-on-chip (SoC), specifically designed for this purpose, on an Ultrascale + Xilinx FPGA, analyzing resource and power consumption, together with system performances. The cryptoprocessor has been then synthesized on a 7-nm CMOS standard-cells technology; performances, complexity, and power consumption information are analyzed and compared with the state of the art. The proposed cryptoprocessor is ready to be embedded within the innovative European Processor Initiative (EPI) chip.

The current Covid-19 pandemic has limited direct contacts among people, since the virus is usually widespread by the drops of saliva. Then, this world outbreak has brought the need to track patients' positions, especially to verify the respect of quarantine regulations for infected people and for their strict contacts. Moreover, the conditions of elderly and high risk patients should be continuously monitored, minimising, at the same time, the exposure of general practitioners. Among the several solutions available on the market, telemedicine seems to be an optimal support for remote monitoring, limiting the contacts between doctors and patients, and fast reaction to worsening of clinical conditions. Telemedicine platforms can also integrate Global Navigation Satellite System technology embedded in wrist devices, to add new functionalities, useful even when the pandemic is over. In this paper, we present the smartwatch integration in the already consolidated E@syCare telemedicine platform, with the aim of tracking patients' positions and monitoring outdoor and indoor fitness sessions. The smartwatch, equipped with WearOS, should have GPS receiver, heart rate sensor and accelerometer and the developed application installed. It randomly collects positions, for patients subjected to quarantine regulations, generating an alarm in case of violation. From the GUI, the user can start fitness sessions, independently or according to the care plan. Positions and fitness sessions are downloaded by the handheld device, and become available for further analysis by the doctors. Nowadays, the platform has been already delivered to 60 patients with the support of European Space Agency (ESA).

In recent years, following the rapid innovation guidelines of most space agencies, there have been major advances in satellite transmitter technologies. Very high performance standards (e.g., DVB-S2, DVB-S2X and CCSDS 131.2-B-1) have been introduced to maximise link utilisation, while carrier frequencies have moved up into the Ku/Ka bands to increase signal bandwidth. Following these trends, system integrators are also pushing the development of architectures that dynamically change the payload symbol rate, thus changing the bandwidth to cover different mission scenarios, within a single implementation. With these conditions, a solution for dynamically changing the symbol rate can be the use of fractional sampling rate converters (FSRC). In this paper the architecture of a massively parallel FSRC is presented for the case where the backpressure functionality for flow control is missing. Implementation considerations and results are taken for a Xilinx Space-Grade Kintex Ultrascale XQRKU060 considering a DVB-S2 generated signal.

Several million people with disabilities exploit power wheelchairs for outdoor mobility on both sidewalks and cycling paths. Especially those with upper limb motor impairments have difficulty reacting quickly to obstacles along the way, creating dangerous situations, such as wheelchair crash or rollover. A possible solution could be to equip the power wheelchair with a neural network-based assisted driving system, able to detect, avoid or warn the users of obstacles. Therefore, a virtual environment is required to simulate the system and then test different neural network architectures before mounting the best performing one directly on board. In this work, we present a simulation framework to train multiple artificial intelligent agents in parallel, by means of reinforcement learning algorithms. The agent shall follow the user's will and identify obstacles along the path, taking the control of the power wheelchair when the user is making a dangerous driving choice. The developed framework, adapted from an existing autonomous driving simulator, has been used to train and test multiple intelligent agents simultaneously, thanks to a customised synchronisation and memory management mechanism, reducing the overall training time. Preliminary results highlight the suitability of the adapted framework for multiple agent development in the assisted driving scenario.

This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2. 52 mW from a 0.9 V supply, is compared to the state-of- the-art sampling buffers, showing linearity improvement.

This paper describes IDEA a database of Italian dysarthric speech produced by 45 speakers affected by 8 different pathologies. Neurologic diagnoses were collected from the subjects' medical records, while dysarthria assessment was conducted by a speech language pathologist and neurologist. The total number of records is 16794. The speech material consists of 211 isolated common words recorded by a single condenser microphone. The words that refer to an ambient assisted living scenario, have been selected to cover as widely as possible all Italian phonemes.The recordings, supervised by a speech pathologist, were recorded through the RECORDIA software that was developed specifically for this task. It allows multiple recording procedures depending on the patient severity and it includes an electronic record for storing patients' clinical data. All the recordings in IDEA are annotated with a TextGrid file which defines the boundaries of the speech within the wave file and other types of notes about the record.This paper also includes preliminary experiments on the recorded data to train an automatic speech recognition system from a baseline Kaldi recipe. We trained HMM and DNN models and the results shows 11.75% and 14.99% of WER respectively.

Following the expansion of the industry requiring small satellites with payloads producing high data rates, the Consultative Committee for Space Data Systems (CCSDS) introduced the CCSDS 131.2-B-1 standard in 2012. The standard combines Serially Concatenated Convolutional Codes (SCCC) with different types of modulation to provide a cost-effective, reliable and efficient payload data transmitter with a high degree of flexibility. This flexibility, due to the number of modulation and coding formats (ModCod), can help designers to better adapt the system configuration to the specific needs of the target. In addition, the use of Adaptive Code and Modulation (ACM) provides the means to adapt payload data transmission to variable channel conditions. To further increase flexibility, the ”EGRET - Next Generation High Rate Telemetry” project has recently defined a proposal to extend the CCSDS SCCC standard to include more efficient transmission schemes. This extension, also called SCCC-X, introduces 10 new ModCods together with a new SCCC-BCH combined encoder and new higher-order modulations (128-APSK and 256-APSK). This document illustrates the entire transmission chain architecture of the SCCC-X telemetry transmitter, highlighting the possible design trade-offs in order to provide a reference for other future developers. Special attention is paid to the analysis of implementation compromises in terms of Bit Error Rate (BER) loss, efficiency, throughput, and source occupation on relevant space-grade FPGAs. In particular, the synthesis results show that SCCC-X can be implemented without changes in the critical path compared to CCSDS 131.2-B-1 and that the implementations are able to achieve more than 450MSym/s on the Xilinx Space-Grade Kintex 7 Ultrascale FPGA and more than 250Msym/s on the Microsemi RTG4 FPGA.

Convolution Neural Networks are a class of deep neural networks commonly used in audio and video elaborations. Their implementation on the edge represents a complex task due to the limited computational power and low power consumption requirement that characterize these applications. In this paper, a fully on-chip Convolutional Neural Network Field Programmable Gate Array-based hardware accelerator is presented. This approach allows to reduce power consumption due to off-chip memory accesses and aims to reduce design time. Advantages and limitations of the proposed architecture are discussed and a trade-off analysis is provided to give intuitions about the feasibility of this method.

Heart failure patients have become an important challenge for the healthcare system, since they represent a medical, social and economic problem. Early heart failure diagnoses can be very useful to improve patients' quality of life and to reduce the resources consumption, but they can be complex for the general practitioners. Data mining and machine learning techniques can really help in this field. The aim of this study is to validate some machine learning models to identify heart failure patients, starting from administrative data, and to make them transparent and interpretable. Despite the lack of clinical data, not available in Italy, but the most employed for the identification of heart failure patients, the results are comparable with the state-of-the-art ones and the models outperform the performances already obtained in Tuscany.

Population aging and the increase of chronic conditions incidence and prevalence produce a higher risk of hospitalization or death. This is particularly high for patients with multimorbidity leading to a great consumption of resources. Identifying as soon as possible high-risk patients becomes an important challenge to improve health care service provision and to reduce costs. Nowadays, population health management, based on intelligent models, can be used to assess the risk and identify these "complex" patients. The aim of this study is to validate machine learning algorithms (Naïve Bayes, Cart, C5.0, Conditional Inference Tree, Random Forest, Artificial Neural Network and LASSO) to predict the risk of hospitalization or death starting from administrative and socio-economics data. The study involved the residents in the Local Health Unit of Central Tuscany.

Nowadays Voice User Interfaces (VUIs) have become popular thanks to their easiness of use that makes them accessible to the elderly and people with disability. Nevertheless, their use in embedded systems for the realization of portable devices is limited by the computation complexity, the memory requirements and power consumption of the keyword spotting (KWS) algorithms, usually based on deep neural networks. In this paper we propose a new algorithm based on convolutional neural networks for the keyword spotting task, that offers a good trade-off among accuracy, power consumption and memory footprint. To select our proposed solution, we compared different neural network architectures to select the best trade-off of these metrics. For further improvements of these performances we implemented our solution on a dedicated hardware platform as Myriad 2 by Movidius. The use of this chip has reduced inference time and energy per inference by 50%.

U-PHOS (Upgraded PHP Only for Space) is a project developed by a team of students from the University of Pisa with the goal to analyze and characterize the behavior of a Pulsating Heat Pipe (PHP), one of the most attractive two phases passive systems for thermal management in space applications. The PHP consists of a sealed serpentine capillary tube filled with a working fluid. The heat is efficiently transported by means of the combined action of phase change and capillary forces, so no extra equipment is required. The project aims at investigating the thermal response of such a device under a milli-gravity condition, in order to assess its effectiveness in space conditions. U-PHOS is one of the selected experiment of the REXUS/BEXUS programme, which allows European university students to carry out scientific and technical experiments on research rockets and balloons, thanks to a bilateral agency agreement between the German Aerospace Centre (DLR) and the Swedish National Space Board (SNSB) in collaboration with ESA. 19 students from the University of Pisa, with different backgrounds, compose the U-PHOS team. Students had the chance to completely design, build and test the experiment, which will flight up to space in March 2017. This paper intends to describe the work done by the students, their organization and how this experience empowered their careers, from both an academic and professional point of view.

The increasing diffusion of chronic diseases represents a challenge for the health systems that have to deal with rising costs caused by the large number of patients. The ICT-enabled telemedicine systems represent a promising solution to provide effective treatments, to reduce hospitalizations and related costs and to improve the patients' quality of life. These systems allow to monitor the clinical status of the patients through self-measured vital signs. The electrocardiogram (ECG) represents one of the most practiced clinical exams in the treatment of chronic patients, but ECG devices currently known for medical purpose are difficult to be used by non-skilled persons, and they are definitively not suitable for such telemedicine systems. This paper introduces a user-friendly and ergonomic device conceived to be used autonomously by the patient to record high quality ECGs. The device acquires the first lead of the ECG from the patient's hands exploiting dry metal electrodes. The device requires few basic actions to be operated and can transmit collected data via Bluetooth connectivity. The developed dedicated API makes also possible an easy integration of the device into telemedicine systems.

Wheelchair Mounted Robotic Arms (WMRA) can be used by people with severe motor skill impairment, such as SMA (Spinal Muscular Atrophy), Cerebral Palsy etc..., in order to achieve daily life tasks. Many of those systems have been presented in literature and are available on the market but they are really expensive and bulky. Instead we propose a simple robotic arm with 4 Degrees of Freedom (DOF), controlled by a cheap embedded platform in order to keep the size and the cost as low as possible. This paper presents the design and evaluation of a simple visual servoing control loop for the robotic arm based on a camera mounted on the arm end effector. A lot of attention has been given to the design process of an effective and more accessible human machine interface, in order to make the arm simply usable by the user. Tests and evaluations were performed on a simplified version of the final system prove the effectiveness of the proposed solution. However further optimization have to be achieved in order to make the whole system really usable in a real-word scenario.

On-Board surround sensors, such as cameras and radars, are used in Advanced Driving Assistance Systems applications to improve the driver safety and comfort. In the meantime, Car-to-Car Communication systems are in the deployment phase and have been tested in huge test fields. In order to compensate the weaknesses and benefit from the strengths of both systems, their information can be fused. In this context, one major challenge is the unambiguous assignment of detected vehicles from different sensors, which is still an open research topic and the major target of this work. An innovative algorithm was first tested in Matlab using recorded data and then implemented on real hardware. The results obtained are promising and, from a spatial point of view, they show already a successful matching of vehicles. Compared with the solutions proposed in literature, the developed demonstrator is innovative, and represents the first step towards a real world application running in real time inside cars. Overall, this work is a useful contribution to active safety and autonomous driving applications based on sensor fusion and a good reference for further research on the topic.

The increasing complexity of automotive networks has led to broad security issues related to human safety. On the other hand, to solve problems of network overload, the automotive world is moving in the direction of using an Ethernet backbone for in-vehicle communications. Therefore, the security of Ethernet protocols for such applications has become a significant concern. The IEEE 802.1X-2010 standard could be a suitable solution for the key management of Ethernet-based encrypted communications. In this work, an efficient hardware accelerator for the intensive sections of the IEEE 802.1X-2010 is presented. The system was synthesized both on a Stratix V FPGA and on a 40nm standard-cell library. The former gives a usage of 3% of the Adaptive Logic Modules (ALMs) while the latter shows an occupation of 55 kgates. On the FPGA, the maximum throughput is 152 Mbps and 1.14 Gbps for the two considered sections of the standard while the standard-cell technology provides a maximum throughput of 457 Mbps and 3.85 Gbps. Results show that this architecture represents a fast and low-area key management solution for Ethernet networks in automotive applications.

European research projects produce many excellent results, and the quality of research papers at DATE and other major European conferences is often outstanding. But how many academic research results in computing technologies and EDA actually make it into industrial practice? In the context of the transition into the Horizon 2020 framework program, the European research community is currently investigating novel ways of stimulating additional academia-industry technology transfer. This special session contributes by discussing concrete transfer experiences and new concepts. Furthermore it will exemplify several success stories from both academic and industrial perspectives. We believe that two major issues currently prevent a wider industrial adoption of research results at European scale: • While most FP7 research projects do provide ambitious exploitation plans, these are rarely implemented to a full extent, because the effort for productization is underestimated and insufficient resources and incentives are available when projects fade out. • There is a lot of emphasis on start-up companies as a primary vehicle for technology transfer. However, the effort of start-up foundation is very high and might not be justified in many cases due to limited market volume. Instead, more focus should be on industrial take-up of specific new technologies or IP generated by research, which does not require large amounts of venture capital. As a consequence, European research needs better mechanisms to provide incentives for technology transfer at small to medium scale. The speakers of this session are experienced actors in this domain. They will point out in a pragmatic way, and using concrete examples, how technology transfer can be initiated and implemented in practice and what are the associated pitfalls and innovation opportunities. The mix of presentations ensures that both academic and industrial viewpoints and concerns are properly addressed. Thus, the session will be of interest to a large audience. Amongst others, it is intended to stimulate more players to engage in international technology transfer. For this purpose, the session will be initiated by a brief presentation of a specific new pilot project (TETRACOM) focused on structured small to medium scale technology transfer. TETRACOM is open to the entire European computing research community and provides both funding and services for bilateral academia-industry collaborations.

This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

The design and the implementation of a flexible and cost-effective embedded system for real-time correction of fish-eye automotive cameras is presented. Nowadays many car manufacturers already introduced on-board video systems, equipped with fish-eye lens, to provide the driver a better view of the so-called blind zones. A fish-eye lens achieves a larger field of view (FOV) but, on the other hand, causes distortion, both radial and tangential, of the images projected on the image sensor. Since radial distortion is noticeable and dangerous, a real-time system for its correction is presented, whose low-power, low-cost and flexibility features are suitable for automotive applications.

The flexibility of an Intelligent Power Switch (IPS) designed in HV-CMOS technology for incandescent lamp in automotive scenarios has been evaluated for the driving of a LED in presence of wiring parasitics. The paper presents how it is possible, through proper reconfiguration of the flexible IPS, to reduce the undesired ringing phenomenon when driving a LED with wiring parasitics thus reducing Electromagnetic Interferences (EMI) and spikes on supply voltage. Electrical simulation and experimental measurements prove the effectiveness of the proposed IPS.

This work presents an orientation tracking system for 6D inertial measurements units. The system was modeled with MathWorks Simulink and experimentally tested with the Cube Demo board by SensorDynamics, used to simulate a 3D gyro and a 3D accelerometer. Quaternions were used to represent the angular position and an Extended Kalman filter was used for the sensor fusion algorithm. The goal was to obtain an integrated system that could be easily integrated within the logic of the new 6D sensor family produced by SensorDynamics. We propose a Kalman filter simplification for a fixed point arithmetic implementation to reduce the system complexity with negligible performance degradation.

This paper presents an innovative and effective approach to design and test a regulator for an automotive alternator with programmable functionalities. The prototype system consists of two different parts: an integrated circuit (IC) and a FPGA. The IC, implemented in austriamicrosystems HVCMOS 0.35 ¿m technology, includes all the high voltage parts and a power switch with very low ON resistance. It is able to manage full reverse polarity on every pin, including the reverse battery condition, and over voltages up to 50 V. The programmability is guaranteed through the FPGA. This prototype system can be used to develop a new type of intelligent smart and flexible regulators which implement many additional programmable functions that give the car maker a better control and allow to reduce vehicle fuel consumption and CO2emissions. In the demonstrator all the implemented functions, including regulation, can be changed during the development phase and many properties, including loop stability, can be checked before releasing a final version of the regulator. The proposed system is also included in a standard brush-holder that can be mounted on Valeo Engine and Electrical System mechatronic alternator and verified directly in a real application.

This work presents a High-Voltage Low-Power CMOS DC-DC buck regulator for automotive applications. The overall system, including the high and low voltage analog devices, the power MOS and the low voltage digital devices, was realized in the Austriamicrosystems 0.35 HVCMOS technology, resulting in a 6.5 mm2die. The regulator is able to manage a supply voltage down to 4.5 V and up to 50 V and generates a fixed regulated output voltage of 5 V or a variable one in the whole automotive temperature range. The regulator sinks only a maximum of 1.8 ¿A of current in standby mode and a maximum of 25 ¿A when no load is connected. It can be used to supply low voltage devices from the battery when low power dissipation and low current consumption is needed. The system output current can be selected in the range 350-700 mA. When a higher output current is needed, it is possible to connect more regulators in parallel multiplying the output current without any problem.

This paper presents an innovative and effective method to improve the performance of a micro mechanical gyroscope by introducing the damping of its sensing quality factor. Indeed the sensing quality factor is a key parameter for the micro mechanical gyroscope dynamic; particularly high sensing quality factor means long settling time, high response overshoot and high sensitivity to external disturbances (shocks and vibrations) that are typical of harsh automotive environment. For this reason micro mechanical gyroscopes employed in automotive environment need high shock and vibration immunity. This paper proposes a solution to reach this goal by adding a ldquovirtual dampingrdquo to the system with an electrostatic feedback technique. This approach has been applied to a real automotive yaw gyro system, and simulations performed using Simulinktrade environment show an appreciable output overshoot reduction, with the benefit of higher vibration immunity, once implemented the feedback technique.

This paper presents an interface device allowing people with upper limbs disabilities to play with console video games. Typical console controllers are equipped with several push-buttons and joysticks often to be operated at the same time, thus becoming a real barrier. Some do-it-yourself solutions exist by adapting commercial controllers to special needs. But, this way, the video game control is totally left to the disabled and very often he is still not able to play the game with his residual functionalities. On top of that such solutions are not even marketable, being non-certified modifications of a commercial device. On the contrary, the system described in this paper is a completely new device connected between the original controller and the console. It allows the connection of the most suitable interface for the specific disability. Thanks to this device the specific interface acts in the same manner as push-buttons and/or joysticks of the original controller. Mapping external sensors functions to the original controller ones is performed by a simple and intuitive procedure. The kind and number of external buttons/sensors is decided according to the user's potential. The original joypad can be used along with the external sensors connected to the device, allowing collaborative playing between one or more disabled persons and another player.

This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 mum bipolar CMOS DMOS (BCD) technology. The proposed solution is designed for frequency applications up to several hundred of KHz and it has a driving current capability up to 50 mA. This work features a design configuration and a digital control to reduce electromagnetic interference (EMI). Moreover it includes short circuit protection, programmability of voltage references and a digital control circuitry implementing mechanism to prevent dangerous failures of the driver. After a deep description of the circuit we show the laboratory results of the half-bridge driver used to drive a 20 KHz antenna.

This paper presents an application based on a hot wire anemometric sensor in MEMS technology in the field of water flow monitoring. New generations of MEMS sensors feature remarkable savings in area, costs and power respect to conventional discrete devices, but as drawback, they require complex electronic interfaces for signal conditioning to achieve high performances and a high reliability. This anemometric sensor implementation has been developed with ISIF, a Platform SoC, aiming to fast prototype a wide range of sensors thanks to its high configurable resources. The presented system achieves good performances with respect to commercial devices, featuring resolution of ±0.35% up to ±1.76% with repeatability roughly ±1% respect to the full scale (0-250 cm/s). Furthermore the proposed system, thanks to the compact size of the sensor, its robustness and its low costs can represent a solution for diffusive monitoring in water distribution networks.

This paper addresses system-level design of time- interleaved analog-to-digital converters (TI-ADCs) for ultra-wide band communications. Design space exploration of a TI successive approximation architecture is performed via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing the main ADC blocks in a 90-nm 1-V CMOS technology. Different speed/resolution scenarios are efficiently investigated and the impact of parallelism on system performance, yield and power consumption is assessed starting from the early design phases, finally enabling the selection of two candidate implementations (a 6-bit 4.6- mW and a 7-bit 8.1-mW ADC targeting 1 GS/s) that effectively trade accuracy for energy efficiency and area.

Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bi-synchronous FIFO structures for frequency conversion is presented. The proposed bridge involves a custom protocol for the conversion of the transmitted data in low frequency and low width bus. Moreover, it allows managing data transmission with two different priority levels. The module is AHB lite compliant with a number of pins equal to the width of the FIFOs (configurable during implementation phase) and two handshaking signals. Output clock frequency and internal FIFOs dimension are user-defined too.

This paper presents a network emulator for rapid prototyping of SpaceWire Intellectual Property cores. SpaceWire is a fault-tolerant high-throughput standard widely used in space and avionic applications. Thanks to its inherent properties, SpaceWire can be effectively adopted for addressing dependability and bandwidth requirements of forthcoming active safety automotive applications. The proposed platform considers both anti-fuse and SRAM FPGA devices. A four-layer software stack ensures full control of prototype features, batch testing and ease of use.

This work presents a low-complexity physical link micro architecture for a mesochronous on-chip communication insensitive to clock skew. This new link architecture, called LIME, integrates a low-latency flow control scheme; this feature may ease the set up of reliable Network-on-Chip infrastructures. The proposed architecture also supports virtual channels that are multiplexed on a single physical link. LIME can be integrated in a conventional digital design flow since it is implemented by means of standard cells only.

Home automation is becoming a field not so futuristic: in fact, the amount of this kind of systems in the marketplace is quickly growing up. Installation of these systems allows improving comfort and security of a house through the integration of the concepts traditionally associated with domestic environment with new generation technologies. The purpose of this paper is to describe ELIK (Easy Living In Kitchen), which is a distributed general-purpose embedded system for domotic applications, developed mainly to bring new features in the kitchen environment.

A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative message passing (iMP) to be run on loopy graph. This technique approximates the maximum-likelihood (ML) estimator, providing a sub-optimal algorithm that searches all possible code phases in parallel, at low complexity and fast acquisition time. This work is addressed to the design of the architecture of an iMP detector, following the implementation methodologies typical of standard low-density parity-check (LDPC) decoders, and demonstrates its benefits in terms of acquisition time and complexity, compared with standard techniques.

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

This paper presents an application of the ISIF chip (intelligent sensor interface), for conditioning a dual-axis low-g accelerometer in MEMS technology. MEMS are nowadays the standard in automotive applications (and not only), as they feature a drastic reduction in cost, area and power, while they require a more complex electronic interface with respect to traditional discrete devices. ISIF is a platform on chip implementation, aiming to fast prototype a wide range of automotive sensors thanks to its high configuration resources, achieved both by full analog / digital IPs trimming options and by flexible routing structures. This accelerometer implementation exploits a relevant part of ISIF hardware resources, but also requires signal processing add-ins (software emulation of digital DSP blocks) for the closed loop conditioning architecture and for performance improvement (for example temperature drift compensation). In spite the short prototyping time, the resulting system achieves good performances with respect to commercial devices, featuring a 0.9 mg/radicHz noise density with 1024 LSB/g sensitivity on the digital output over a +/- 2g FS, and an offset drift over 100degC range within 30 mg, with 2% of FS sensitivity drift. Miniboards have been developed as product prototypes, consisting of a small PCB with ISIF and accelerometer dies bonded together, firmware embedded in EEPROM and communication transceivers

The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automotive vision and safety warnings require in-car reliable communication backbones with the capability to handle large amount of data at high speeds. To cope with this issue and driven by the experience of aerospace systems, the SpaceWire standard, recently proposed by the European space agency (ESA), can be introduced in the automotive field. The SpaceWire is a serial data link standard which provides safety and redundancy and guarantees to handle data-rates up to hundreds of Mbps. This paper presents the design of configurable SpaceWire router and interface hardware macrocells, the first in state of the art compliant with the newest standard extensions, Protocol Identification (PID) and remote memory access protocol (RMAP). The macrocells have been integrated and tested on antifuse technology in the framework of an ESA project. The achieved performances of a router with 8 links, 130 Mbps data-rate, 1.5 W power cost, meet the requirements of future automotive electronic systems. The proposed networking solution simplifies the connectivity, reducing also the relevant volume and mass budgets, provides network safety and redundancy and guarantees to handle very high bandwidth data flows not covered by current standards as CAN or FlexRay

Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations.

This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy).

This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.

This paper describes a scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes. The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard. The decoder works in pipeline, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding. Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations. The synthesis on 65 nm CMOS technology with low-power standard- cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185 mW.

The cost reduction is a key factor in the preparation of new scientific missions for space exploration and therefore in the design of Space Craft (S/C). In order to achieve this goal, investigations are carried out in order to verify the usability of components off the shelf (COTS) and technologies widely used in the industry. In this frame, a test campaign has been performed at the European Space and Technology Centre (ESTEC) of the European Space Agency (ESA). The campaign aims at characterizing the CAN bus in terms of EMC, specifically radiated emission, in a typical configuration for a small satellite, evaluating the effect of different configurations in its performances. The CAN bus has been selected because it is considered a good alternative to the reliable MIL-STD-1553B bus, often used as control bus of a Space Craft.

This paper describes the design activity for the digital baseband processing of a prototype receiver for the Galileo system. According to the applied hardware-software partitioning, the high rate elaborations have been implemented on a dedicated hardware, a Xilinx Virtex2 FPGA, while the remaining low rate processing has been programmed on an Analog Device DSP. A customarily designed prototype board has been used to validate the receiver under real working conditions: a dynamic GPS and Galileo scenarios. Particularly, the paper focus on the receiver Digital Channel, which is the critical core of the FPGA, from VHDL modeling to hardware implementation and testing.

The principle of "layered decoding" is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed. Two different strategies are considered to solve the problem and the related architectures presented: one more straightforward, and based on the use for the soft output of the last value originated in a layer; the other based on the computation of the variation (or delta) of the soft output metrics to allow concurrent updates. Then, as in architecture-first approach, the performance is assessed for several widths of the layer, which remarks the robustness of the delta-mechanism to high parallelisation factors. As in the exact layered decoding, the average boost of two times in the convergence speed is shown

A general architecture suitable for interfacing several kinds of sensors for automotive applications is presented. A platform based design approach is pursued to improve system performance while minimizing time-to-market. The platform is composed of an analog front-end and a digital section. The latter is based on a microcontroller core (8051 IP by Oregano) plus a set of hardware dedicated to the complex signal processing required for sensor conditioning. The microcontroller also handles the communication with external devices (such as a PC) for data output and fast prototyping. A case study is presented concerning the conditioning of a gyro yaw rate sensor for automotive applications. Measured performance results outperform current state-of-the-art commercial devices.

Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).

This paper presents a design methodology suitable for the cost-effective and real-time implementation of nonlinear image processing algorithms. Starting from high-level functional descriptions the proposed optimization flow simplifies the designer's duty to achieve a low complexity and low power realization in CMOS technology (FPGA and/or ASIC) with low accuracy loss for the implemented algorithm. As an application case study the paper describes the design of a system, based on a Retinex-like algorithm, to improve the visual quality of images acquired in bad lighting conditions.

This paper presents a 2048 bit, rate 1/2 soft decision decoder for a new class of codes known as turbo Gallager codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 /spl mu/m standard-cell CMOS technology.

In this paper, a digital RFI (radio frequency interference) canceller for DMT (discrete multitone modulation)-based VDSL (very high-speed digital subscriber line) systems is presented. The adopted algorithm is optimized in terms of performance vs. complexity and size of the involved memories. High level, maximum precision system simulations showed the effectiveness of the cancellation scheme, considering VDSL performance parameters such as bit rate and efficiency in counteracting performance degradation due to RFI. The canceller has been implemented as a hardware macro-cell: the design space already explored at algorithm level to meet a good complexity/performance trade-off, has been deeply investigated during the bit true analysis to fix the finite numeric representation, the micro-architecture definition and the final technology mapping. Results of logic synthesis on a standard cells 0.18 /spl mu/m CMOS technology are reported, in terms of area and energy consumption.

This paper presents a prototyping environment suited to fast identify, trim and verify a digital sensor interface in the automotive field, and to make early performance evaluations before proceed towards the final ASIC product. The overall platform is composed by hardware blocks and software tools suitable for the design space exploration, while a proper verification methodology is being adopted to guarantee the correct system behavior. In order to tune the platform architecture with an application case and at the same time to demonstrate its flexibility, two case examples are being examined.

This paper presents the design and the main performance results of a single-ASIC implementation of the recently proposed extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for code division multiple access (CDMA) transmission. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in blind mode, i.e., it only requires knowledge of the timing of the wanted user's signature code, and it is therefore very well-suited for integration into handheld single-user terminal demodulators. The implementation of the interference-mitigating detector is based on a patented optimized architecture which leads, in 0.25-/spl mu/m CMOS technology, to a roughly 25 Kgate plus 23-Kbit RAM single-chip ASIC supporting chip rates up to 4 Mchip/s with a maximum internal clock frequency of 32.768 MHz. The main design drivers are thoroughly discussed, and the relevant performance results are compared to the theoretical behavior. A possible extension to multirate CDMA systems adopting orthogonal variable spreading factor (OVSF) sequences is also addressed.

The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for ever faster and more reliable real-time signal processing operations to be performed by highly integrated and low-power consumption digital receivers. One of the most critical signal processing tasks to be performed by the DS/SS-CDMA receiver is signal presence detection and code epoch estimation. This paper deals with the design and realization of an application-specific integrated-circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in packet DS/SS-CDMA receivers operating in a satellite or terrestrial radio network. In particular, we show how a parallel acquisition circuit can be effectively implemented on a single-chip with a 1.0-/spl mu/m CMOS technology according to the specifications of the ARCANET Ku-band CDMA VSAT satellite network sponsored by the European Space Agency (ESA). It is shown that the ASIC performance closely follows analytical predictions.