Recently, the requirement of storing digital data has been growing rapidly; however, the conventional storage medium cannot satisfy these huge demands. Fortunately, thanks to biological technology development, storing digital data into deoxyribonucleic acid (DNA) has become possible in recent years. Furthermore, because of the attractive features (e.g., high storing density, long-term durability, and stability), DNA storage has been regarded as a potential alternative storage medium to store massive digital data in the future. Nevertheless, reading and writing digital data over DNA requires a series of extremely time-consuming processes (i.e., DNA sequencing and DNA synthesis). More specifically, among the two costs, the writing cost is the predominant cost of a DNA data storage system. Therefore, to enable efficient DNA storage, this article proposes an index management scheme for reducing the number of accesses to DNA storage. Additionally, this article introduces a new DNA data encoding format with VERA (Version Editing Recovery Approach) to reduce the total writing bits while inserting and deleting the data. To the best of our knowledge, this work is the first work to provide a total data management solution for DNA storage. According to the experimental results, the proposed design with VERA can reduce the cost by 77% and improve the performance by 71% compared to the append-only methods.

Random forest has been widely used to classifying objects recently because of its efficiency and accuracy. On the other hand, nonvolatile memory has been regarded as a promising candidate to be a part of a hybrid memory architecture. For achieving the higher accuracy, random forest tends to construct lots of decision trees, and then conducts some post-pruning methods to fell low contribution trees for increasing the model accuracy and space utilization. However, the cost of writing operations is always very high on non-volatile memory. Therefore, writing the to-be-pruned trees into non-volatile memory will significantly waste both energy and time. This work proposed a framework to ease such hurt of training a random forest model. The main spirit of this work is to evaluate the importance of trees before constructing it, and then adopts different writing modes to write the trees to the non-volatile memory space. The experimental results show the proposed framework can significantly mitigate the waste of energy with high accuracy.

Due to cyber-physical systems, a large-scale multiversion indexing scheme has garnered significant attention in recent years. However, modern multiversion indexing schemes have significant drawbacks (e.g., heavy write traffic and weak key- or version-range-query performance) while being applied to a computer system with a nonvolatile random access memory (NVRAM) as its main memory. Unfortunately, with the considerations of high memory cell density and zero-static power consumption, NVRAM has been regarded as a promising candidate to substitute for dynamic random access memory (DRAM) in future computer systems. Therefore, it is critical to make a multiversion indexing scheme friendly for an NVRAM-based system. For tackling this issue with modern multiversion indexing schemes, this article proposes a write-reduction multiversion indexing scheme with efficient dual-range queries. According to the experiments, our scheme effectively reduces the amount of write traffic generated by the multiversion indexing scheme to NVRAM. It offers efficient dual-range queries by consolidating the proposed version forest and the multiversion tree.

With the latest advance in the non-volatile random-access memory (NVRAM), NVRAM is widely considered as the mainstream for the next-generation storage mediums. NVRAM has numerous attractive features, which include byte addressability, limited idle energy consumption, and great read/write access speed. However, owing to the high manufacturing cost of NVRAM, the incentive of deploying NVRAM in consumer electronics is lowered due to the consideration of profitability. To resolve the profitability issue and bring the benefits of NVRAM into the design of consumer electronics, avoiding storing duplicate data on NVRAM becomes a crucial task for lowering the demand and deployment cost of NVRAM. Such observation motivates us to propose a data deduplication extended file system design (DeEXT) to boost the profitability of NVRAM via the concept of dual-chunking data deduplication while considering the characteristics of NVRAM and duplicate data content. The proposed DeEXT was then evaluated by real-world data deduplication traces with encouraging results.

Owing to the explosive growth of data volume, high areal density storage technologies have been proposed in the past few years. Among them, shingled magnetic recording (SMR) has been regarded as the most promising candidate to replace current conventional hard disk drive based on the perpendicular magnetic recording technology. However, SMR technology not only brings large capacity storage devices but also results in terrible random access performance. For increasing the random access performance of SMR, solid-state hybrid drive (SSHD) seems a possible solution in storage system development. Nevertheless, when an SMR-based SSHD is adopted to a large-scale data management system, a severe performance degeneration will happen because an indexing scheme for access efficiency always maintains data in the large-scale data management system. More specifically, jointly managing indexing keys and data values on an SSHD drive will result in the massive amount of write amplification because of read-merge-write operations and garbage collection processes. Based on such motivations, this work proposed a total solution, namely XsB+-tree, to establish a high-performance B+-tree-based data management scheme for key-value store systems. To the best of our knowledge, this work is the first work to discuss the total solution for the key-value store over an SMR-based SSHD. According to our experimental results, XsB+-tree can improve the access time by 80% on average and prolong the lifetime of SSD up to 19%.

Owing to flash memory constraints, a garbage collection (GC) mechanism hurts flash storage lifespan and performance since it generates a massive amount of write data to flash memory. To add insult to injury, all GC designs cannot identify disused data from valid data; therefore, all valid data, including disused data, will be rewritten to flash memory during the GC process. Fortunately, a flash storage vendor recently proposed a new write command to bring extra information to flash translation layer (FTL). Thanks to the new write command, the lifetime information of data can be brought from a host-side system to an FTL management layer for disused data identification. By such observations, this work proposes a dual-time referencing FTL (DTR-FTL) design to deal with disused data and minimize the overhead of GC by referring to data lifetime information and block retention time.

Nonvolatile random access memory (NVRAM) is becoming a popular alternative as the memory and storage medium in battery-powered embedded systems because of its fast read/write performance, byte-addressability, and nonvolatility. A well-known example is phase-change memory (PCM) that has much longer life expectancy and faster access performance than NAND flash. When NVRAM is considered as both main memory and storage in battery-powered embedded systems, existing page cache mechanisms have too many unnecessary data movements between main memory and storage. To tackle this issue, we propose the concept of “union page cache,” to jointly manage data of the page cache in both main memory and storage. To realize this concept, we design a partial page cache strategy that considers both main memory and storage as its management space. This strategy can eliminate unnecessary data movements between main memory and storage without sacrificing the data integrity of file systems. A series of experiments was conducted on an embedded platform. The results show that the proposed strategy can improve the file accessing performance up to 85.62% when PCM used as a case study.

Nonvolatile random access memory (NVRAM) has been regarding a promising technology to replace DRAM as the main memory in embedded systems owing to its nonvolatility and low idle power consumption. However, due to the asymmetric read/write costs and limited lifetime of NVRAM, most of the existing fundamental algorithms are not NVRAM-friendly with their write pattern and write intensiveness. Thus, existing fundamental algorithms for NVRAM embedded devices has been revealed. For instance, as the sorting algorithm is one of the most fundamental algorithms, most of the existing sorting algorithms are not NVRAM-friendly because they impose heavy write traffic [i.e., O(n lgn)] on main memory, where n is the number of unsorted elements. To resolve this issue, this article proposes a write-once sorting algorithm, namely B*-sort, to reduce the amount of write traffic on NVRAM-based main memory. B*sort adopts a brand-new concept, i.e., tree-based sort, inspired by the binary-search-tree structure to achieve the write-once property which can guarantee the optimal endurance during the sorting process. According to the experimental results, B*-sort can achieve significant performance improvement for sorting on NVRAM-based systems.

Shingled magnetic recording (SMR) is regarded as a promising technology for resolving the areal density limitation of conventional magnetic recording hard disk drives. Among different types of SMR drives, drive-managed SMR (DM-SMR) requires no changes on the host software and is widely used in today’s consumer market. DM-SMR employs a shingled translation layer (STL) to hide its inherent sequential-write constraint from the host software and emulate the SMR drive as a block device via maintaining logical to physical block address mapping entries. However, because most existing STL designs do not simultaneously consider the access pattern and the data update frequency of incoming workloads, those mapping entries maintained within the STL cannot be effectively managed, thus inducing unnecessary performance overhead. To resolve the inefficiency of existing STL designs, this article proposes a demand-based STL (DSTL) to simultaneously consider the access pattern and update frequency of incoming data streams to enhance the access performance of DM-SMR. The proposed design was evaluated by a series of experiments, and the results show that the proposed DSTL can outperform other SMR management approach by up to 86.69% in terms of read/write performance.

Growing demand for key-value store applications is building a strong momentum for the commercialization of key-value hard disk drives. To achieve better performance, flash-based solid state drive is the next ideal candidate for commercialization in the foreseeable future. However, the existing fixed-sized management strategies of flash-based devices would potentially result in low storage space utilization when managing variable-sized key-value data. In addition, the low storage space utilization would further lead to the degradation of device performance, due to low invalid data space reclamation efficiency. The space utilization issue motivates this paper to propose a key-value flash translation layer design to improve storage space utilization as well as the performance of the key-value solid state drives. A series of experiments was conducted to evaluate the proposed design, and the experiment results of space utilization and device performance are very encouraging.

Due to the fast access performance, byte-addressability, and non-volatility of non-volatile random access memory (NVRAM), NVRAM has emerged as a popular candidate for the design of memory/storage systems on mobile computing systems. For example, the latest 3D xPoint memory could be a kind of NVRAM with much longer life expectancy than NAND flash and could ease the possible endurance issue. When NVRAM is considered as both main memory and storage in mobile computing systems, existing page cache mechanisms introduce too many unnecessary data movements between main memory and storage. To resolve this issue, we propose the concept of "union page cache," which jointly manages data of the page cache in both main memory and storage. To realize this concept, a partial page cache strategy is designed to consider both main memory and storage as its management space and to eliminate unnecessary data movements between main memory and storage without sacrificing the data consistency of file systems. Experimental results show that the proposed strategy can boost the file accessing performance upto 85.62% when using PCM as a case study.

Due to the decreasing endurance of flash chips, the lifetime of flash drives has become a critical issue. To resolve this issue, various techniques such as wear-leveling and error correction code have been proposed to reduce the bit error rates of flash storage devices. In contrast to these techniques, we observe that minimizing write amplification is another promising direction to enhance the lifetime of a flash storage device. However, the development trend of large-page flash memory exacerbates the write amplification issue. In this work, we present a compression-based management design to deal with compressed data updates and internal fragmentation in flash pages. Thus, it can minimize write amplification by only updating the modified part of flash pages with the support of data reduction techniques; and the reduced write amplification degree is more significant when the flash page size becomes larger due to the development trend. This design is orthogonal to wear-leveling and error correction techniques and thus can cooperate with them to further enhance the lifetime of a flash device. Based on a series of experiments, the results demonstrate that the proposed design can effectively improve the lifetime of a flash storage device by reducing write amplification.

Non-volatile random-access memory (NVRAM) is regarded as a great alternative storage medium owing to its attractive features, including low idle energy consumption, byte addressability, and short read/write latency. In addition, multi-level-cell (MLC) NVRAM has also been proposed to provide higher bit density. However, MLC NVRAM has lower energy efficiency and longer write latency when compared with single-level-cell (SLC) NVRAM. These drawbacks could lead to higher energy consumption of MLC NVRAM-based storage systems. The energy consumption is magnified by existing journaling file systems (JFS) on MLC NVRAM-based storage devices due to the JFS's fail-safe policy of writing the same data twice. Such observations motivate us to propose a multi-write-mode journaling file systems (mwJFS) to alleviate the drawbacks of MLC NVRAM and lower the energy consumption of MLC NVRAM-based JFS. The proposed mwJFS differentiates the data retention requirement of journaled data and applies different write modes to enhance the energy efficiency with better access performance. A series of experiments was conducted to demonstrate the capability of mwJFS on a MLC NVRAM-based storage system.

Non-volatile random-access memory (NVRAM) becomes a mainstream storage device in embedded systems due to its favorable features, such as small size, low power consumption, and short read/write latency. Unlike dynamic random access memory (DRAM), NVRAM has asymmetric performance and energy consumption on read/write operations. Generally, on NVRAM, a write operation consumes more energy and time than a read operation. Unfortunately, current mobile/embedded file systems, such as EXT2/3 and EXT4, are very unfriendly for NVRAM devices. The reason is that current mobile/embedded file systems employ a journaling mechanism for increasing its data reliability. Although a journaling mechanism raises the safety of data in a file system, it also repeatedly writes data to a data storage while data is committed and checkpointed. Though several related works have been proposed to reduce the amount of write traffic to NVRAM, they still cannot effectively minimize the write amplification of a journaling mechanism. Such observations motivate us to design a two-phase write reduction journaling file system called wrJFS. In the first phase, wrJFS classified data into two categories: Metadata and user data. As the size of metadata is usually very small (few bytes), byte-enabled journaling strategy will handle metadata during commit and checkpoint stages. In contrast, the size of user data is very large relative to metadata; thus, user data will be processed in the second phase. In the second phase, user data will be compressed by hardware encoder to reduce the write size and managed compressed-enabled journaling strategy to avoid the write amplification on NVRAM. Moreover, we analyze the overhead of wrJFS and show that the overhead is negligible. According to the experimental results, the proposed wrJFS outperforms other journaling file systems even though the experiments include the overhead of data compression.

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches$10^{4}$.

With the advanced technology in persistent random access memory (PRAM), PRAM such as three-dimen-sional XPoint memory and Phase Change Memory (PCM) is emerging as a promising candidate for the next-generation medium for both (main) memory and storage. Previous works mainly focus on how to overcome the possible endurance issues of PRAM while both main memory and storage own a partition on the same PRAM device. However, a holistic software-level system design should be proposed to fully exploit the benefit of PRAM. This article proposes a union storage file system (UnistorFS), which aims to jointly manage the PRAM resource for main memory and storage. The proposed UnistorFS realizes the concept of using the PRAM resource as memory and storage interchangeably to achieve resource sharing while main memory and storage coexist on the same PRAM device with no partition or logical boundary. This approach not only enables PRAM resource sharing but also eliminates unnecessary data movements between main memory and storage since they are already in the same address space and can be accessed directly. At the same time, the proposed UnistorFS ensures the persistence of file data and sanity of the file system after power recycling. A series of experiments was conducted on a modified Linux kernel. The results show that the proposed UnistorFS can eliminate unnecessary memory accesses and outperform other PRAM-based file systems for 0.2--8.7 times in terms of read/write performance.

The strong momentum of key-value store applications drives the commercialization of key-value-specific hard disk drives. To achieve higher degree of performance, the specific flash-based solid state drives would be also commercialized for key-value store applications in the foreseeable future. However, the existing fixed-sized management strategies of flash-based devices would potentially result in low storage space utilization on managing variable-sized key-value data. This problem inspires this paper to propose a key-value flash translation layer (KVFTL) design to improve the storage space utilization of the key-value-specific solid state drives (KVSSDs). A series of experiments was conducted to evaluated the proposed design, and the experimental results on space utilization and device performance are very encouraging.

As the volume of data stored by Big data and Cloud services continues to grow, both academia and industry are seeking for high-performance storage systems. Recently, with the recent advances in write-optimized indexes (WOI), WOI-based file systems can now outperform conventional file systems with orders of magnitude on random writes, metadata updates, and small file creation. Based on the B-tree structure, WOI-based file systems can not only process data faster than the conventional B-tree but also improve the range query performance. However, the write amplification of these WOI-based file systems becomes a serious performance overhead when adopting flash storage as underlying storage devices due to the recursive entry update behavior. To mitigate the write amplification problem of WOIbased file systems, we propose a flash-friendly WOI design to reduce the number of write requests on flash storage. To evaluate the performance of the proposed design, we adapt B+-tree as a case study and the experimental results are promising.

Non-volatile memory (NVM) has widely participated in the evolution of the next-generation memory architecture by way of being the substitution of the main memory. To cope with the problem of asymmetric read/write speeds of NVM, several excellent researches have been proposed to reduce the number of writes to the NVM-based main memory. Nevertheless, most of these existing approaches do not take the cache-line-based access behavior between the processor and the main memory into consideration. Thus, in order to essentially improve the access performance of the NVM-based memory architecture, this work aims to optimize the cache-line-based access performance over the NVM-based memory architecture based on the special access patterns in many popular internet of things (IoT) and in-memory database applications. Our experiments based on the well-known Gem5 full system simulator reveal that, compared to other existing representative approaches, the proposed design can effectively reduce the total execution time of insertion by 20.92~55.20% and improve the execution time of query by 2.06~23.36%.

Non-volatile random-access memory (NVRAM) becomes a mainstream storage device in embedded systems due to its favorable features, such as small size, low power consumption, and short read/write latency. On NVRAM, a write operation consumes more energy and time than a read operation. However, current mobile/embedded file systems (e.g., EXT2/3 and EXT4) are very unfriendly for NVRAM devices. The reason is that a journaling mechanism writes the same data twice during data commitment and checkpoint. Such observations motivate this paper to design a two-phase write reduction journaling file system called wrJFS. In the first phase, wrJFS classified data into two categories: Metadata and user data. Metadata will be handled by partial byte-enabled journaling strategy, and user data will be processed in the second phase. In the second phase, user data will be compressed by hardware encoder so as to reduce the write size, and managed compressed-enabled journaling strategy to avoid the write amplification. The experimental results show that the proposed wrJFS can reduce the size of the write request by 89.7% on average, compared with the original EXT3.

The growing demands of large capacity fash-based storages have facilitated the down-scaling process of NAND fash memory. Among NAND fash technologies, 3D charge trap fash is regarded as one of the most promising candidates. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exaggerated in the 3D charge trap fash with the fast-growing number of layers. In this study, a progressive performance boosting strategy is proposed to boost the performance of 3D charge trap fash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving access performance of 3D charge trap flash.

In our previous work, a simulation framework was proposed to focus on imitating the behavior of wireless charging vehicles (WCVs) and wireless sensor networks (WSNs) because current mainstream simulators have very limited support on simulation of WCVs. The WCV is an integration of a mobile vehicle and a wireless power transfer broadcaster, which is used to recharge sensors wirelessly to prolong the lifetime of sensor networks. In the study of WCVs, simulators are extensively used to study the routing algorithms and behaviors of WCVs because it is very costly to build a WSN testbed and many specifications are not standardized. However, mainstream WSN simulators require researchers to develop and integrate their WCV modules. Therefore, the previously proposed framework aims to provide a simple framework for simulating of wireless power transfer and mobile vehicles. In this study, to further strength the usability of the proposed simulation framework, a graphic user interface is introduced to allow users to assign sensors' location and specify simulation parameters.

To accommodate the sheer volume of data in the era of Big Data and Cloud Computing, both new storage medium technologies and high-performance file systems are proposed. For storage medium, Shingled Magnetic Recording (SMR) increases the areal density by overlapping adjacent tracks so as to provide larger storage capacity. On the other hand, write-optimized indexes (WOI) file systems are also studied and can now outperform conventional file systems with orders of magnitude. However, the main drawback of SMR is the random-write restriction because random-write operations will cause the extra overhead of rewriting data stored in overlapped tracks. The rewriting overhead is amplified by the recursive entry update behavior of WOI-based file systems. Therefore, the rewriting issue becomes a serious performance overhead when adopting SMR drives as underlying storage devices for WOI-based file systems. To mitigate the write amplification problem when deploying WOI-based file systems on SMR disks, this paper proposes the update-overhead-aware caching policy to reduce the update overhead with the help of flash-based storage devices. To evaluate the performance of the proposed design, the B+-tree as a case study. The experimental results are promising.

Since the mid-2000s, mobile/embedded computing systems conventionally have limited computing power, Random Access Memory (RAM) space, and storage capacity due to the consideration of their cost, energy consumption, and physical size. Recently, some of these systems, such as mobile phone and embedded consumer electronics, have more powerful computing capability, so they manage their data in small flash storage devices (e.g., Embedded Multi Media Card (eMMC) and Secure Digital (SD) cards) with a simple file system. However, the existing file systems usually have low space utilization for managing small files and the tail data of large files. In this work, we thus propose a dynamic tail packing scheme to enhance the space utilization of file systems over flash storage devices in embedded computing systems by dynamically aggregating/packing the tail data of (small) files together. To evaluate the benefits and overheads of the proposed scheme, we theoretically formulate analysis equations for obtaining the best settings in the dynamic tail packing scheme. Additionally, the proposed scheme was implemented in the file system of Linux operating systems to evaluate its capability. The results demonstrate that the proposed scheme could significantly improve the space utilization of existing file systems.

The support of secure deletion on formatting a file system is to make sure that when a file system is formatted, there is no way to get any file content back again. Due to the fast-growing storage capacity, the performance of secure deletion to file systems on resource-constrained flash storage devices has become a critical issue. In contrast to the existing works that take a long time on overwriting/resetting all the file contents of a file system, we propose an efficient secure deletion scheme to securely delete all the contents of a file system without rewriting file contents. Thus, secure deletion to file systems can be efficiently achieved and can be independent of the device capacity and file systems. A series of experiments was conducted with realistic workloads to evaluate the capability of the proposed scheme. The results show that the proposed scheme achieves secure deletion with limited performance overheads in most cases.

Summary The concept of green storage in cluster computing has recently attracted enormous interest among researchers. Consequently, several energy‐efficient solutions, such as multi‐speed disks and disk spin down methods, have been proposed to conserve power in storage systems and improve disk access. Some researchers have assessed their proposed solutions via simulations, while others have used real‐world experiments. Both methods have advantages and disadvantages. Simulations can more swiftly assess the benefits of energy‐efficient solutions, but various measurement errors can arise from procedural shortcomings. For instance, many power simulation tools fail to consider how heat increases the power overhead of disk operations. Some researchers claim that their modeling methods reduce the measurement error to 5% in the single disk model. However, the demand for large‐scale storage systems is growing rapidly. Traditional power measurement using a single disk model is unsuited to such systems because of their complex storage architecture and the unpredictability of numerous disks. Consequently, a number of studies have conducted real machine experiments to assess the performance of their solutions in terms of power conservation, but such experiments are time consuming. To address this problem, this study proposes an efficient simulation tool called Benchmark Analysis Software for Energy‐efficient Solution (BASE), which can accurately estimate disks' power consumption in large‐scale storage systems. We evaluate the performance of BASE on real‐world traces of Academia Sinica (Taiwan) and Florida International University. BASE incorporates an analytical method for assessing the reliability of energy‐efficient solutions. The analytical results demonstrate that the measurement error of BASE is 2.5% lower than that achieved in real‐world experiments involving energy‐estimation experiments. Moreover, the results of simulations to assess solution reliability are identical to those obtained through real‐world experiments. Copyright © 2015 Copyright © 2015 John Wiley & Sons, Ltd.

Phase-change memory (PCM) is a promising candidate as a storage medium to resolve the performance gap between main memory and storage in battery-powered mobile computing systems. However, it is more expensive than flash memory, and thus introduces a more serious storage capacity issue for low-cost solutions. This issue is further exacerbated by the fact that existing file systems are usually designed to trade space utilization for performance over block-oriented storage devices. In this work, we propose a multi-grained block management strategy to improve the space utilization of file systems over PCM-based storage systems. By utilizing the byte-addressability and fast read/write feature of PCM, a methodology is proposed to dynamically allocate multiple sizes of blocks to fit the size of each file, so as to resolve the space fragmentation issue with minimized space and management overheads. The space utilization of file systems is analyzed with consideration of block sizes. A series of experiments was conducted to evaluate the efficacy of the proposed strategy, and the results show that the proposed strategy can significantly improve the space utilization of file systems.

Recently, phase change memory (PCM) has become a promising candidate to replace dynamic RAM as main memory due to its low power consumption, fast I/O performance, and byte addressability. Accompanied with the merits, the adoption of PCM may suffer from its physical characteristic of limited write endurance. Wear leveling is a well-known approach to address this issue. For PCM main memory, the design of wear leveling should stress operation efficiency and overhead reduction. Nevertheless, conventional designs are usually dedicated to prolonging the lifetime of PCM in the best effort. In this paper, we propose a novel perspective that, instead of valuing PCM lifetime exploitation as the first priority, we turn to satisfy the product warranty period. With such a paradigm shift, the management overhead of wear-leveling mechanisms could be reduced so as to achieve further enhancement of operation efficiency. To this end, we propose a warranty-aware page management design that introduces novel criteria used to determine the state of a page by taking both the product warranty period and the write cycles of a page into consideration. Theoretical analysis is also conducted to investigate the properties and performance of the proposed management. To show the effectiveness of the proposed design, we collected real traces by running SPEC2006 benchmarks with different write intensity workloads. The experimental results showed that our design reduced the overhead to one-third that of the state-of-the-art designs while still providing the same level of performance.

Recently, many applications and users rely on cloud storage services, such as Google drive, Dropbox, iCloud and Sky drive, to store private files and system data, and cloud storage services must thus be reliable and secure. To increase reliability, previous studies have proposed a variety of erasure coding algorithms for data fault tolerance for use in storage systems. Although these data fault tolerance mechanisms increase data reliability, implementation also increases storage system costs and energy consumption due to data redundancy. However, to date energy-efficient schemes have only been developed based on a RAID architecture, and none have been implemented using an erasure coding algorithm. To address this issue, this study proposes an energy-aware I/O framework with a quality-of-service (QoS) aware data reconstruction scheduler for erasure coding algorithms, called the EEC-scheme. This approach reduces storage system energy consumption and decreases response times for user requests when the system restores failed disks. A series of experiments show that the proposed scheme can significantly reduce power consumption in storage systems.

The lifetime of wireless sensor networks are constrained by its limited battery capacity. Therefore, the lifetime is widely regard as a bottleneck of technique of wireless sensor network. Recently, the emerging breakthrough in wireless power transfer technique is expected to eliminate the power constraint bottleneck. In this paper, we propose an intelligent wireless charging vehicle (IWCV) strategy to resolve above problem in a dynamic and scalable approach. The IWCV strategy includes an intelligent routing strategy to traverse the sensor network topology and charging their battery to prolong their lifetime. What makes IWCV different to previous studies is that IWCV can still work even if the topology changes by re-computing the traversing route and stop time for each node in a relative short amount of time, compared with the time needed to find the shortest Hamiltoaian cycle. With the scalable and dynamic feature of IWCV, one can change their sensor network topology without down time to reconfigure the wireless charging vehicle while still maintain low energy consumption during traveling and charging in dynamic network topologies.

Summary A distributed environment requires a monitoring system to oversee the operation of various distributed nodes. A monitoring service is crucial because it ensures a high‐quality computing environment and a reliable service. The interface and framework determine the effectiveness of a monitoring system. This paper uses the concept of user‐adaptive visualization to design its interface and proposes a flexible modular framework. Designers can use the proposed modular framework to flexibly extend existing modules, design visual interfaces to satisfy user requirements, and improve system failover schemes. The implementation of such a monitoring system for monitoring data preservation nodes is also provided. The system including fault‐tolerance and notification functions supports full monitoring services for Storage Resource Broker (SRB) or integrated Rule‐Oriented Data System (iRODS) based systems. The experimental results show that the proposed framework is suitable for data preservation services and is robust and responsive when faced with system failures. Copyright © 2014 John Wiley & Sons, Ltd.

Previous studies proposed energy-efficient solutions, such as multispeed disks and disk spin-down methods, to conserve power in their respective storage systems. However, in most cases, the authors did not analyze the reliability of their solutions. According to research conducted by Google and the IDEMA standard, frequently setting the disk status to standby mode will increase the disk’s Annual Failure Rate and reduce its lifespan. To resolve the issue, we propose an evaluation function called E 3 SaRC (Economic Evaluation of Energy Saving with Reliability Constraint), which considers the cost of hardware failure when applying energy-saving schemes. We also present an adaptive write cache mechanism called CacheRAID. The mechanism tries to mitigate the random access problems that implicitly exist in RAID techniques and thereby reduce the energy consumption of RAID disks. CacheRAID also addresses the issue of system reliability by applying a control mechanism to the spin-down algorithm. Our experimental results show that the CacheRAID storage system can reduce the power consumption of the conventional software RAID 5 system by 65% to 80%. Moreover, according to the E 3 SaRC measurement, the overall saved cost of CacheRAID is the largest among the systems that we compared.

Improving the disk I/O performance is always a critical research issue in cloud computing platforms, especially for cloud computing platforms with distributed data-intensive workloads. To resolve the problem of poor disk I/O, in this paper, we propose a novel scheduling framework in the Xen-based hypervisor. In our framework, we employ a locality-aware scheduler with a deadline constraint and provide a basic QoS controller to guarantee the throughput of the cloud platform. The experimental results show that our solution increases the IOPS of Xen-based cloud platform by 9%-13% compared to the solution of early-deadline-first (EDF), deadline scheduling algorithm or Flubber. Moreover, according to the schedulability test, our solution can improve the miss deadline ratio significantly, compared to the EDF scheduling algorithm and Flubber.

The thriving growth in mobile consumer electronics makes energy efficiency in the embedded system design an important and recurring theme. Phase Change Memory (PCM) has shown its potential in replacing DRAM as the main memory option due to its (65%) reduced energy requirements. However, when considering the usage of PCM main memory, its write endurance becomes a critical issue, and wear leveling design is a common approach to resolve this issue. Even though the wear leveling design should stress operation efficiency and overhead reduction, existing wear leveling strategies designed for PCM main memory are usually dedicated to prolonging the lifetime of PCM. In this paper, we propose the perspective that, instead of valuing PCM lifetime exploitation as the first priority, we should turn to satisfy the product warranty period. To this end, further enhancement of operation efficiency and reduction of management overhead could be achieved. We thus propose a warranty-aware page management design to enhance the operation efficiency for managing the endurance issue in PCM. To show the effectiveness of the proposed design, we collected real traces on fiasco. OC by running SPEC2006 benchmarks with different write intensity workloads. The experiment results showed that our design reduced the overhead to one third of that of the state-of-the-art designs while still providing the same level of performance.

Although wireless sensor devices usually have limited power, they are widely deployed in various applications, such as in remote sensing for forestry applications, military monitoring, and animal behavior. Most sensor applications deploy sensor devices in natural environments, such as forests, tunnels, and caves, to monitor targets and to collect data. To permanently monitor target environments, the battery in a sensor device needs to be recharged as its battery capacity the limited. A wireless charging vehicle uses wireless charging technology to prolong the lifetime of sensor network applications by recharging the device's battery. The wireless charging vehicle is usually equipped with a large capacity battery, an electromagnetic field, and wheels such that it can move throughout an entire sensor network to charge sensors' batteries. When the wireless charging vehicle does not need to recharge any sensor's battery, it stays at a service station to recharge its own battery. Hence, a wireless charging vehicle needs to consider two things: sensor network lifetime, and vehicle energy consumption. This work proposes a geometric solution called the Dynamic Path Generation Scheme (DPG-Scheme) to arrange the Wireless Charging Vehicle's (WCV's) travelling path while minimizing a vehicle's energy consumption and maximizing a sensor network's lifetime. The DPG-Scheme is based on the space-filling curve solution. Based on the properties of the space-filling curve, the DPG-Scheme uses space-filling curves as a space-filling curve heuristic for the NP-hard Euclidean travelling salesperson problem. The DPG-Scheme can reduce computational time when computing a wireless sensor network's (WSN's) travelling path and a new path is calculated rapidly during sensor network topology changes.

Embedded computing systems usually have limited computing power, RAM space, and storage capacity due to the consideration of their cost, energy consumption, and physical size. Some of them such as sensor nodes and embedded consumer electronics only have a small-sized flash memory as their storage with a (simple) file system to manage their data, which are usually of small sizes. However, the existing file systems usually have low space utilization on managing small files and the tail data of large files. In this work, we propose a dynamic tail packing scheme to optimize the space utilization of file systems by dynamically aggregating/packing the tail data of (small) files together. The proposed scheme was implemented in the file system of Linux operating systems to evaluate its capability. The results demonstrate that the proposed scheme could significantly improve the space utilization of existing file systems.

The concept of green storage in cluster computing has generated a great deal of interest among researchers in recent years. As a result, several energy-efficient solutions, such as multi-speed disks and disk spin down methods, have been proposed to conserve power in storage systems and improve disk access. Some researchers evaluate their solutions via simulations, while others utilize real-world experiments. Both methods have advantages and disadvantages. To address the problem, we propose an efficient simulation tool called BASE, which can accurately estimate the power consumption of disks in large-scale storage systems. We evaluate the performance of BASE on real-world traces from Academia Sinica (Taiwan) and Florida International University. BASE incorporates an analytical method for evaluating the reliability of energy-efficient solutions. Our analysis results show that the measurement error of BASE is 2.5% lower than that achieved in real-world experiments on energy estimation. Moreover, the results of simulations performed to evaluate a solution's reliability are the same as those derived by real-world experiments.

Virtualization is a critical technology issue in cloud computing. Virtualization technology faces two major challenges, namely, poor I/O throughput and long latency for data access. To address the issues, we present a distributed deadline modification SCAN mechanism called DDM-SCAN. We integrate the DDM-SCAN mechanism to Xen-based cloud platform. The result of our simulations show DDM-SCAN improve the I/O response time of Xen-based cloud platform 20% comparing to Flubber [1] mechanism and it also guarantee same or better quality of service (QoS) as compared with Flubber mechanism in Xen-based hypervisor. In advance, this paper provides more easy method to implement DDM-SCAN on Xen-based hypervisor rather than Flubber mechanism.

Internet of Things (IoT) has been widely researched over the past decade. Recently, many research results of IoT related to emergency system, smart building and medical system, etc. The key for IoT applications are the ability to interact with physical world through computation, communication, and machine control. However, each sensor device in IoT cannot conveniently communicate with other terminal devices through internet protocol. So, it is necessary to establish protocol translation stack or equipment between two WSN groups. That is very inefficient and high overhead cost of network construction. The development of micro-IP (uIP) solves this problem. The uIP reduce cost of protocol translation and it also realizes the machine to machine (M2M) concept in wireless sensor network. Therefore, this paper proposes a solution for porting uIP library to the wireless sensor network devices and presents the integration of a speaker module and IPv6 ready sensor device. We also propose a safe building application based on the integrated system to help people escaping from disaster environment. In conclusion, our contributions are building an IPv6 ready wireless sensor network environment and develop a safe building system to make the concept of IoT in IPv6 network environment come true.

Real-time systems using rate-monotonic fixed priority scheduling can be checked for schedulability either by sufficient but pessimistic schedulability conditions or by exact testing. Exact testing provides a more precise result but may not be performed in polynomial time. Audsley et al. proposed one of the earliest methods by iteratively deriving the response times of jobs. Other researchers have improved the exact test method by using different initial values for testing. In this paper, we propose new initial values of p, - p, , and f in a task set of i tasks, where p, is the period of task Tl. We show that the new initial values can significantly improve the efficiency of exact testing. These period-dependent initial values can also be used for the schedulability test of multiframe task models and effectively reduce the number of iterations for testing.

The real-time multiframe task model first studied by Mok and Chen assumes that the computation times of a periodic task vary instance by instance. They have derived an utilization bound for verifying the schedulability of multiframe task sets. Their schedulability test has since been improved by other researchers. In this paper we use the information about the relative period ratios between tasks in a system to derive a new schedulability condition. By considering the smallest and the largest period values in a system, we can show that the RM schedulability bound can be improved significantly. This method also can be applied to other test methods studied earlier to improve the schedulability of real-time multiframe systems.

Real-time systems using rate monotonic fixed priority scheduling can be checked for schedulability either by pessimistic schedulability conditions or exact testing. Exact testing provides a more precise result but cannot always be performed in polynomial time. Audsley et al. proposed one of the earliest methods by iteratively deriving the job response times. Other researchers have improved the efficiency of their exact test method by using different initial values. All currently proposed initial values do not use the relationship between task periods. In this paper we define initial values using the largest and the second largest periods in a system. We show that the new initial values can significantly improve the exact test.

Many optimal uniprocessor schedulers, such as earliest deadline first (EDF) and rate monotonic (RM), do not have a good schedulability bound on multiprocessor systems. In this paper, we study an on-line algorithm earliest deadline first until Zero laxity (EDZL) for multiprocessor systems. A set of tasks scheduled by EDZL is scheduled using EDF until a job experiences a zero laxity. To avoid the job from missing its deadline, the priority of the job is immediately promoted to the highest priority. We derive the schedulability bound of 3/2+\umax-1/2\ for two-processor systems, where umaxis the maximum utilization of an individual task in the given task set. We also discuss the best known upper bound and lower bound on EDZL schedulability conditions.

Feasibility and schedulability problems have received considerable attention from the real-time systems research community in recent decades. Since the publication of the Liu and Layland bound, many researchers have tried to improve the schedulability bound of the RM scheduling. The LL bound does not make any assumption on the relationship between any of the task periods. In this paper we consider the relative period ratios in a system. By reducing the difference between the smallest and the largest virtual period values in a system, we can show that the RM schedulability bound can be improved significantly. This research has also proposed a system design methodology to improve the schedulability of real time system with a fixed system load.

Data broadcast is an efficient information delivery model that can deliver information to a large population simultaneously. In this paper, we propose two efficient algorithms to broadcast real-time and non-real-time data together. The goal of our algorithms is to reduce the average response time of non-real-time data under the constraint that all real-time data must meet their deadlines. The experimental results show that our proposed algorithms can reduce the average response time while guaranteeing the timing constraints.