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Phil Garrison

dblp:25/2230 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 61% Processor architecture and microarchitecture · 39%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache		 0.011983
Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983
Memory systems › cache › CPU cache
instruction cache		 0.011983
Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983
Processor architecture and microarchitecture › instruction fetch
instruction fetch unit		 0.011983
Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983
Processor architecture and microarchitecture › instruction set architecture
RISC		 0.011983
Architecture of a VLSI Instruction Cache for a RISC · ISCA 1983
YearPublicationVenuePosition
1983 Architecture of a VLSI Instruction Cache for a RISC
abstract
A cache was first used in a commercial computer in 1968,1 and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit.
David A. Patterson 0001, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, Korbin S. Van Dyke
 ISCA2