Pattern matching for network intrusion/prevention detection requires extremely high throughput with frequent updates to support new attack patterns. Most of current hardware implementations have outstanding performance over software implementations. However, the requirement for dynamic update pattern set is still challenging for hardware researchers. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher performance. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the latest Snort rule-set, an open source network intrusion detection/prevention system, and achieve the highest utilization in terms of SRAM per character and logic cells per character at 17 bits/character and 0.043 logic cells/character, respectively on major Xilinx Virtex architectures. Compared to others, ours is much more efficient than any other Xilinx FPGA architectures.

This paper presents a reconfigurable processor array for the similarity search of up to sixteen DNA query sequences against a large database. Based on the recently proposed space-time mapping methodology, the processor array is implemented using a Xilinx Virtex-4 XC4VLX60 FPGA on the AVNet ADS-XLX-V4-LX-EVL60 board. The proposed system can sustain a high computation throughput rate with lower data transfer speed from the host database than others up to sixteen folds via a USB 2.0 interface.

ClustalW is the most widely used tool for aligning multiple protein or nucleotide sequences. The alignment is achieved via three stages: pairwise alignment, guide tree generation and progressive alignment. This paper analyzes and enhances a multithreaded implementation of ClustalW called ClustalW-SMP for higher throughput. Our goal is to maximize the degree of parallelism on multithreading ClustalW called MultiThreading-ClustalW (MT-ClustalW). As a result, bioinformatics laboratories are able to use this MT-ClustalW with much less energy consumption on multicore and SMP (symmetric multiprocessor) machines than that of PC clusters. The experiment results show that the MT-ClustalW framework can achieve a considerable speedup over the sequential ClustalW and original multithreaded ClustalW-SMP implementations

Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.

The picture quality of video frames encoded at very low-bit rates often suffers from both blocking and ringing artifacts. We present two post-processing methods to mitigate the visual quality degradation caused by these artifacts. To reduce the blocking artifact of decoded images, we substitute IDCT for the lapped orthogonal transform embedded inverse discrete cosine transform (le-IDCT). On the other hand, we post-process the decoded video frames using a nonlinear robust filter to reduce the ringing artifact. Extensive simulation results indicated significant improvement in both objective and subjective visual qualities. The computation overhead incurred due to these quality enhancement operations is quite moderate, and can be easily optimized to achieve real-time operation.

A systolic motion estimation processor (MEP) core architecture implementing the full-search block-matching (FSBM) algorithm is presented. A unique feature of this MEP architecture is its support of frame-level pipelined operation. As such, it is possible to process pixels from consecutive frames without any processor idle time. It is designed so that no data broadcasting operations are required, and achieves 100% fully pipelined computation. It compares favorably with existing MEP architectures in terms of both performance and complexity of architecture.

Low bit-rate multimedia communication over wireless channels has received much attention recently. A key challenge in low bit-rate wireless communication is the very high error rate during transmission. This demands error resilient services that exhibit graceful performance degradation while operating in a highly noisy channel. Among video, audio and other multimedia communication modalities, we focus on the error-resilient transmission of video signals over wireless channels in this paper. Specifically, efforts in developing H.263++ Annex V error resilient data partitioning with reversible variable length code (RVLC) are described in detail. The performance over error-prone channels is analyzed and the effectiveness of the syntax is demonstrated with extensive simulations.

This paper presents the generalized lapped biorthogonal transform embedded inverse discrete cosine transform (ge-IDCT) as an alternative to the IDCT. The ge-IDCT with nonlinear weighting in the embedded transform domain can reconstruct the signal with alleviated blockishness. Additional complexity, imposed by the replacement, is trivial thanks to an efficient lattice structure. The proposed ge-IDCT is applied in the JPEG still image compression standard to demonstrate its validity.