Demo Data from EDBT 2026 / reviewers in the wild / expert
Bruno Galilée
dblp:25/2481
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 87% Hardware accelerators and domain-specific architectures · 13% | |
| Computer graphics and multimedia
1 paper |
Image and video processing · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Image and video processing
image segmentation |
0.1 | 1 | 2007 | Parallel Asynchronous Watershed Algorithm-Architecture · IEEE Trans. Parallel Distributed Syst. 2007 |
Image and video processing › image segmentation › region-based segmentation
watershed segmentation |
0.1 | 1 | 2007 | Parallel Asynchronous Watershed Algorithm-Architecture · IEEE Trans. Parallel Distributed Syst. 2007 |
Parallel and multicore computing › parallel algorithms › parallel algorithm design
asynchronous parallel algorithms |
0.1 | 1 | 2007 | Parallel Asynchronous Watershed Algorithm-Architecture · IEEE Trans. Parallel Distributed Syst. 2007 |
Parallel and multicore computing
parallel algorithms |
0.1 | 1 | 2007 | Parallel Asynchronous Watershed Algorithm-Architecture · IEEE Trans. Parallel Distributed Syst. 2007 |
Hardware accelerators and domain-specific architectures
algorithm-hardware co-design |
0.0 | 1 | 2007 | Parallel Asynchronous Watershed Algorithm-Architecture · IEEE Trans. Parallel Distributed Syst. 2007 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Fast and accurate TLM simulations using temporal decoupling for FIFO-based communicationsabstractA known approach to improve the timing accuracy of an untimed or loosely timed TLM model is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a heterogeneous many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications. Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal Vivet |
DATE | 3 |
| 2007 | Parallel Asynchronous Watershed Algorithm-Architecture
Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 2002 | Watershed parallel algorithm for asynchronous processors arrayabstractA joint algorithm-architecture analysis leads to a new version of picture segmentation system adapted to multimedia mobile terminal constraints. The asynchronous processors network, with a granularity level of one processor per pixel, based on data flow model, takes less than 10 /spl mu/s to segment a SQCIF $88*72 pixels - image (about 2000 times faster than the classical sequential watershed algorithms). The main originality of the proposed algorithm is only one global synchronization point is needed in order to complete the segmentation transformation, instead of the three (or more) classical points: minima detection, labelization and flooding. Our system tends to cope with multimedia mobile phones constraints, i.e. real time computing circuit, low power. We have simulated and validated this system thanks to "SystemC" library; VHDL synchronous prototyping shows up results accordingly. Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon |
ICME (1) | 1 |