Jim Lawson

dblp:25/2768 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 50% GPUs and heterogeneous computing · 50%
Computer graphics and multimedia
1 paper
Rendering · 100%
Software engineering, system software, and programming languages
1 paper
Programming languages and type systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Rendering › shading
shading models
0.011990
A language for shading and lighting calculations · SIGGRAPH 1990
GPUs and heterogeneous computing
graphics accelerator
0.011987
Parallel Computers for Graphics Applications · ASPLOS 1987
Processor architecture and microarchitecture
SIMD
0.011987
Parallel Computers for Graphics Applications · ASPLOS 1987
Programming languages and type systems
domain-specific languages
0.011990
A language for shading and lighting calculations · SIGGRAPH 1990

Methods — techniques the papers use, named apart from their topics

control flow constructs · 0.0built-in functions · 0.0
YearPublicationVenuePosition
2017 Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
abstract
Enabled by modern languages and retargetable compilers, software development is in a virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; but hardware development practices lag far behind. We hypothesize that existing hardware construction languages (HCLs) and novel hardware compiler frameworks (HCFs) can put hardware development on a similar evolutionary path by enabling new hardware libraries to be independent of underlying process technologies including FPGA mappings. We support this claim by (1) evaluating the degree with which Chisel, an existing HCL, can support powerfully parameterized libraries, and (2) introducing the concept and implementation of an HCF that uses an open-source hardware intermediate representation, FIRRTL (Flexible Intermediate Representation for RTL), to transform target-independent RTL into technology-specific RTL. Finally, we evaluate many hardware compiler transformations, including simplifying transformations, analyses, optimizations, instrumentations, and specializations, which demonstrate the power of a combined HCL and HCF approach.
Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Colin Schmidt 0001, Chick Markley, Jim Lawson, Jonathan Bachrach
ICCAD10
1990 A language for shading and lighting calculations
abstract
A shading language provides a means to extend the shading and lighting formulae used by a rendering system. This paper discusses the design of a new shading language based on previous work of Cook and Perlin. This language has various types of shaders for light sources and surface reflectances, point and color data types, control flow constructs that support the casting of outgoing and the integration of incident light, a clearly specified interface to the rendering system using global state variables, and a host of useful built-in functions. The design issues and their impact on the implementation are also discussed.
Pat Hanrahan, Jim Lawson
SIGGRAPH2
1987 Parallel Computers for Graphics Applications
abstract
Specialized computer architectures can provide better price/performance for executing image processing and graphics applications than general purpose designs. Two processors are presented that use parallel SIMD data paths to support common graphics data structures as primitive operands in arithmetic expressions. A variant of the C language has been implemented to allow high level language coding of user applications on these processors. High level programming support is designed into the processor architecture that implements parallel object data typing and parallel conditional evaluation in hardware.
Adam Levinthal, Pat Hanrahan, Mike Paquette, Jim Lawson
ASPLOS4