This paper presents a method to convert gate-level combinational loop into an acyclic circuit, if the combinational loop is not oscillatory. Combinational loops breach design methodologies, because they can involve undesirable circuit behavior and can possibly lead to oscillations based on the external stimuli to the loops. However, for designs compiled using automated synthesis-compiler, these loops are very likely to appear in the generated gate-level designs. We present a modeling of combinational loops as state holding elements and break non oscillatory loops using a level sensitive latch. Apart from modeling combinational loops consisting of gates, the algorithm also converts the loops through design latches. The increase in design area, due to the loop conversion, has an upper bound of twice the size of the original feedback path. However, in case of multiply nested feedback paths, each path is treated separately. Unlike previous work that converts cyclic combinational logic where the feedback is not exercised, this paper presents an algorithm to identify the stateful "latch" behavior in a class of feedback logic (non-oscillatory, monotonic). A conversion algorithm replaces such feedback logic by an equivalent circuit comprising explicit latches and acyclic combinational logic. The replacement circuit has an identical behavior as the original stateful feedback logic.

The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the register-transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface

A transaction-based layered architecture providing for 100% portability of a C-based testbench between simulation and emulation is proposed. Transaction-based communication results in performance which is commensurate with emulation without a hardware target. Testbench portability eliminates duplicated effort when combining system level simulation and emulation. An implementation based on the IKOS VStation emulator validates these architectural claims on real designs.

While ASIC devices of a decade ago primarily contained synchro-nous circuitry triggered with a single clock, many contemporary architectures require multiple clocks that operate asynchronously to each other. This multi-clock domain behavior presents significant functional verification challenges for large parallel verification sys-tems such as distributed parallel simulators and logic emulators. In particular, multiple asynchronous design clocks make it difficult to verify that design hold times are met during logic evaluation and causality along reconvergent fanout paths is preserved during signal communication. In this paper, we describe scheduling and synchro-nization techniques to maintain modeling fidelity for designs with multiple asynchronous clock domains that are mapped to parallel verification systems. It is shown that when our approach is applied to an FPGA-based logic emulator, evaluation fidelity is maintained and increased design evaluation performance can be achieved for large benchmark designs with multiple asynchronous clock domains.

The presence of multiple clock domains presents significant challenges for large parallel verification systems such as parallel simulators and logic emulators that model both design logic and memory. Specifically, multiple asynchronous design clocks make it difficult to verify that design hold times are met during memory model execution and causality along memory data/control paths is preserved during signal communication. We describe new scheduling heuristics for memory-based designs with multiple asynchronous clock domains that are mapped to parallel verification systems. The scheduling approach scales to an unlimited number of clock domains and converges quickly to a feasible solution if one exists. It is shown that when the technique is applied to an FPGA-based emulator containing 48MB of SRAM, evaluation fidelity. is maintained and increased verification performance is achieved for large, memory-intensive circuits with multiple asynchronous clock domains.

TIERS is a new pipelined routing and scheduling algorithm implemented in a complete VirtualWireTM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.