This paper presents the details of our speech quality prediction system submitted to the Conferencing Speech-2022 challenge.The challenge involved the task of non-intrusive speech quality assessment intended for online conferencing applications.We propose two approaches for speech quality prediction in this work.The first approach uses a combination of deep convolutional neural network (CNN) and LSTM neural network with Kullback-Leibler (KL) loss function and cross entropy (CE) loss function for estimating the mean opinion scores (MOS).Our second approach uses transformer based encoder network before applying attention pooling.We observe that our proposed second method gives significant improvements compared to our first method as well as on the baselines provided by the challenge organizers with respect to Pearson Correlation Coefficient (PCC) and Spearman Rank Correlation Coefficient (SRCC) along with reductions in root mean square error (RMSE).The model is also seen to generalize for unseen data resources on the evaluation dataset.

Exhaustive property checking, design defect isolation and functional coverage measurement are some of the key challenges of design verification. This paper describes how an assertion based approach successfully addressed these challenges for the verification of an enterprise class chip-multi-threaded (CMT) SPARC™ microprocessor. Methodology and experiences are discussed and recommendations are made on how to incorporate this into the design verification process. Experience with using assertion checks for formal verification as well as simulation based verification is presented, which is part of over 100 person year design verification effort.

The AltiVec/sup TM/ technology is an extension to the PowerPC architecture/sup TM/ which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low-cost, low-power processor based on the acclaimed PowerPC 750/sup TM/ microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

There are many parallel signal processing algorithms that are I/O bound. For such algorithms, fast data and program diStribution is very important. In this paper we study a new strategy for data: distribuUonfiom host to MIMD hypercube nodes. This strategy, based on scatteeng on hypercubes of decremental dimensions, perform much better than other strategies known today. It optimizes both the host and node utilization and also exploits the possible overlap in data sent i o different nodes.