Memory interference occurs when two or more concurrent data requests are addressed to the same main memory bank. In vector superconductors, this problem is serious due to the periodic interaction among vectors accesses, and can significantly reduce memory bandwidth and overall system performance. Two techniques can be used to reduce the effects of memory interference. First, vector data can be placed in the main memory such that, when accessed concurrently, the vectors do not interfere with one another. Second, buffers can be used at the memory banks to hold conflicting requests and to allow vector streams to continue to access other banks. Conditions for arbitrary numbers of vector streams to access an interleaved memory system without conflict are derived. It is shown that when three or more vector streams must be accessed concurrently, vector data placement to avoid conflicts becomes increasingly difficult, and that bank buffers can be effective under these conditions in increasing the effective memory bandwidth.>

The authors analyze and identify a basic deficiency of a class of random interleaving schemes (LINEAR), which use linear transformation techniques to achieve randomization. Since all bank addresses generated by these methods are random, constrained only by the bijective property, more conflicts tend to occur than in the more common MODULO method. Also LINEAR lacks the capability of MODULO to move several conflicting vector streams to a conflict-free steady state. To correct these deficiencies, a new class of random interleaving schemes called RANDOM-H that hash only the higher-order address bits is proposed. Unlike LINEAR, the RANDOM-H schemes randomize selectively, while retaining some of the advantages of MODULO. It is shown that RANDOM-H has a higher probability of accessing a vector without conflict than LINEAR. An an example of RANDOM-H, a method called MASH is presented that combines module interleaving with a multiplicative hashing function for randomization.>

The performance of three commercial vector computers, the Cray X-MP/48, IBM 3090/400, and Alliant FX/8, for simulating logic circuits at gate level is compared. Experiments that assume zero- and unit-delay models demonstrate that certain key architectural features, especially, the presence of a scalar cache, have an adverse impact on the potential speedup. Consequently, the achievable speedup due to vectorization of simulation code, while still substantial, is less than expected. The results indicate that concurrent operation of multiple CPUs in vector mode in machines such as the Alliant FX/8 might be the most cost-effective speedup technique for logic simulation on current vector processors.>