Heterogeneous computing technologies, such as multi-core CPUs, GPUs and FPGAs can provide significant performance improvements. However, developing applications for these technologies often results in coupling applications to specific devices, typically through the use of proprietary tools. This paper presents SHEPARD, a compile time and run-time framework that decouples application development from the target platform and enables run-time allocation of tasks to heterogeneous computing devices. Through the use of special annotated functions, called managed tasks, SHEPARD approximates a task's performance on available devices, and coupled with the approximation of current device demand, decides which device can satisfy the task with the lowest overall execution time. Experiments using a task parallel application, based on an in-memory database, demonstrate the opportunity for automatic run-time task allocation to achieve speed-up over a static allocation to a single specific device.

The heterogeneous computing revolution continues unabated. Yet despite the vast number of naïve users in possession of bespoke software hoping to embrace the opportunities that this revolution has wrought, few approaches proposed in current literature can guide such users in these efforts. The most appropriate choice would appear to be a (semi-)automating compiler. However, these typically target a single device-type and demand the unguided use of directives. Consequently, they are of little use when naïve users are seeking answers to more fundamental questions, such as: which fragments of a program can/should be parallelized, which device should each fragment target, and what speedup will be attained. To this end, this paper expands on previous work and proposes Paralysis - an extensible guidance environment, tiered for varying programmer competencies with support for static and dynamic analysis techniques. At the highest level, guided user experiences are paramount. At the lowest level, underlying functionality is exposed as a set of plug-ins, ensuring longevity. A partial prototype, built atop the Cetus infrastructure, is described. It is used to analyze two serial programs for CUDA execution - the DFT and the Box Blur Filter. Speedups of 15x and 22x are achieved on the basis of the analysis.

Introducing automation into a managed environment includes significant initial overhead and abstraction, creating a disconnect between the administrator and the system. In order to facilitate the transition to automated management, this paper proposes an approach whereby automation increases gradually, gathering data from the task deployment process. This stored data is analysed to determine the task outcome status and can then be used for comparison against future deployments of the same task and alerting the administrator to deviations from the expected outcome. Using a machine-learning approach, the automation tool can learn from the administrator's reaction to task failures and eventually react to faults autonomously.

Latent semantic indexing (LSI) is commonly used to match queries to documents in information retrieval (IR) applications. This paper presents a new philosophy for LSI, investigating the use of various hybrid approaches and presents a novel evaluation strategy based on the use of image processing tools. The authors evaluate the use of the discrete cosine transform (DCT) and Cohen Daubechies Feauveau 9/7 (CDF9/7) wavelet transform as a pre-processing step for the singular value decomposition (SVD) step of the LSI system. In addition, the effect of different threshold types on the search results is examined. The results show that accuracy can be increased by applying both transforms as a pre-processing step, with better performance for the hard-threshold function. The choice of the best threshold value is a key factor in the transform process.

Skip Tree Graph is a novel, distributed, data structure for peer-to-peer systems that supports exact-match and order-based queries such as range queries efficiently. It is based on skip trees, which are randomised balanced search trees equivalent to skip lists and designed to provide improved concurrency. Skip tree graphs constitute an extension of skip graphs enhancing their performance in both, exact-match and range queries. Moreover, skip tree graph maintains the underlying balanced tree structures using randomization and local operations, which provides a greater degree of concurrency and scalability.

A self-organising, peer-to-peer, network model, iXChange, is presented. Peers share information, such as usage history and centres of interest, to self organise into semantically clustered groups and intelligently elect super peers using a neural network. Super peers can efficiently route queries based on a small world model and demonstrate a strong self organisational capability using ontology based interest representations. Preliminary results show that the neural network super peer election architecture can be trained in an acceptably low amount of time resulting in successful autonomous election of efficient and reliable super peers.

Efficient access to distributed and dynamic multidimensional data is vital for applications in large, heterogeneous, decentralized, resource-sharing environments such as grids and peer-to-peer systems. Most systems providing this functionality assume homogeneous participants. This paper proposes HADAS, an access structure exploiting heterogeneity to build a self-aware adaptive information system.

This paper describes two approaches suitable for an FPGA implementation of Walsh-Hadamard transforms. These transforms are important in many signal processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both distributed arithmetic ROM and accumulator structure, and a sparse matrix factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. Distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.

Image texture segmentation is an important problem and occurs frequently in many image processing applications. Although, a number of algorithms exist in the literature. Methods that rely on the use of expectation-maximisation algorithm are gaining a growing interest. The main feature of this algorithm is that it is capable of estimating the parameters of mixture distribution. This paper presents a novel unsupervised algorithm based on expectation-maximisation algorithm where the analysis is applied on vector data rather than the grey level. This is achieved by defining a likelihood function which measures how the estimated features are fitting the present data. Experimental results on images containing various synthetic and natural textures have been carried out and a comparison with existing and similar techniques has shown the superiority of the proposed method.

A compiler for a Pascal-based language Actus is described. The language is suitable for the expression of the type of parallelism offered by both array and vector processors. The implementation described is for the Cray-1 computer. An objective of the implementation has been to construct an optimizing compiler which can be readily adapted for a range of array and vector processors. As a result the machine-dependent sections of the compiler have been clearly identified.

Abstract This paper describes, in an informal manner, the programming language ACTUS which was designed to facilitate programming array processing and vector processing ‘supercomputers’. ACTUS extends the program structuring and data structuring facilities of Pascal to the synchronous parallel environment as represented by array and vector processor architectures. A knowledge of Pascal is assumed and only the parallel features of ACTUS are described.

Abstract This paper describes the development of a program to solve the Henderson and Snowdon ‘Telegrams Problem’, the program being expressed as a set of communicating sequential processes (Hoare7).