Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

A modified decoupled sense amplifier (MDSA) and modified decoupled sense amplifier with NMOS foot-switch is proposed for improved sensing in differential SRAM for low-voltage operation at the 22-nm technology node. The MDSA and MDSANF both offer notable improvements to read delay over conventional voltage and current sense amplifiers. At an operating voltage of 0.8 V, the MDSA exhibited a reduced delay of 28.6%, 41.79%, 37.74%, and 30.94% compared to modified clamped sense amplifier (MCSA), double tail sense amplifier (DTSA), modified hybrid sense amplifier (MHSA), and conventional latch-type sense amplifier (LSA), respectively. Similarly, the MDSANF demonstrated a delay reduction of 26.13%, 39.78%, 35.58%, and 28.55% over MCSA, DTSA, MHSA, and LSA, respectively. To validate the performance, the MDSA and MDSANF are evaluated using the variation in delay and power consumption across various supply voltages, process corners, input differential bit line voltage (ΔV BL ), bit line capacitance (C BL ), and the sizing of decoupling transistors. Monte Carlo simulations were conducted to analyse the impact of voltage threshold variations on transistor mismatch which leads to an increased occurrence of read failures and a decline in SRAM yield. The performance analysis of various voltage and current sense amplifiers is presented along with MDSA and MDSANF. Area consideration for selection of sensing scheme is important and as such layout of MDSA and MDSANF was performed conforming to the design rules and estimated area for MDSA is 0.297 μm 2 whereas MDSANF occupies 0.5192 μm 2 .

A large number of significant assets are available online in English, which is frequently translated into native languages to ease the information sharing among local people who are not much familiar with English. However, manual translation is a very tedious, costly, and time-taking process. To this end, machine translation is an effective approach to convert text to a different language without any human involvement. Neural machine translation (NMT) is one of the most proficient translation techniques amongst all existing machine translation systems. In this paper, we have applied NMT on two of the most morphological rich Indian languages, i.e. English-Tamil and English-Malayalam. We proposed a novel NMT model using Multihead self-attention along with pre-trained Byte-Pair-Encoded (BPE) and MultiBPE embeddings to develop an efficient translation system that overcomes the OOV (Out Of Vocabulary) problem for low resourced morphological rich Indian languages which do not have much translation available online. We also collected corpus from different sources, addressed the issues with these publicly available data and refined them for further uses. We used the BLEU score for evaluating our system performance. Experimental results and survey confirmed that our proposed translator (24.34 and 9.78 BLEU score) outperforms Google translator (9.40 and 5.94 BLEU score) respectively.

Particle filters (PFs) are sequential Monte Carlo methods that use particle representation of state‐space model to implement the recursive Bayesian filter for non‐linear and non‐Gaussian systems. Owing to this property, PFs have been extensively used for object tracking in recent years. Although PFs provide a robust object tracking framework, they suffer from shortcomings. Particle degeneracy and particle impoverishment brought by the resampling step result in abysmal construction of posterior probability density function (PDF) of the state. To overcome these problems, this work amalgamates two characteristics of population‐based heuristic optimisation algorithms: exploration and exploitation with PF implementing dynamic resampling method. The aim of optimisation is to distribute particles in high‐likelihood area according to the cognitive effect and improve quality of particles, while the objective of dynamic resampling is to maintain diversity in the particle set. This work uses very efficient spider monkey optimisation to achieve this. Furthermore, to test the efficiency of the proposed algorithm, experiments were carried out on one‐dimensional state estimation problem, bearing only tracking problem, standard videos and synthesised videos. Metrics obtained show that the proposed algorithm outplays simple PF, particle swarm optimisation based PF, and cuckoo search based PF, and effectively handles different challenges inherent in object tracking.