Demo Data from EDBT 2026 / reviewers in the wild / expert
Stephen W. Melvin
dblp:25/4491
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-authorSoftware engineering, systems software and programming languages · 3 · 2 first-authorTheory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 55% Parallel and multicore computing · 27% Performance modeling and evaluation · 18% | |
| Software engineering, system software, and programming languages
2 papers |
Operating systems · 74% Compilers and program optimization · 26% |
Topics — the 5 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › task scheduling
dynamic scheduling |
0.0 | 1 | 1991 | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques · ISCA 1991 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 1991 | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques · ISCA 1991 |
Processor architecture and microarchitecture
speculative execution |
0.0 | 1 | 1991 | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques · ISCA 1991 |
Operating systems
kernel instrumentation |
0.0 | 1 | 1988 | The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels · SIGMETRICS 1988 |
Compilers and program optimization
instruction scheduling |
0.0 | 1 | 1991 | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques · ISCA 1991 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0tracing · 0.0microcode instrumentation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | Handling of packet dependencies: a critical issue for highly parallel network processorsabstractNetwork processors are being asked to perform increasingly complex operations on packets of information at faster and faster rates. Because processor performance and memory cycle times are not keeping up with this demand, there is a fundamental need for simultaneous processing of multiple packets, and the degree of this parallelism is increasing. Sometimes a dependency exists between two packets currently being operated on, and as the ratio of packet processing time to packet transmission time increases, these dependencies are more likely to impact performance. Thus, the way packet dependencies are handled will become critical. In this paper we show that there is potentially a dramatic difference in performance between optimal and non-optimal solutions. We argue that this is the key challenge that must be addressed in highly parallel network processors. We discuss how work in thread level speculation relates to this problem and describe a practical hardware implementation that requires little or no changes to software and with near optimal performance. Stephen W. Melvin, Yale N. Patt |
CASES | 1 |
| 1991 | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software TechniquesabstractABSTMCTIt has been suggested that non-scientific code has very little parallelism not already exploited by existing processors.In this paper we show that contrary to this notion, there is actually a significant amount of unexploited parallelism in typical general purpose code.In order to exploit this parallelism, a combination of hardware and software techniques must be applied.We analyze three techniques: dynamic scheduling, speculative execution and basic block enlargement.We will show that indeed for narrow instruction words 1itde is to be gained b y appl yi ng these techniques.However, as the number of simultaneous operations increases, it beeomes possible to achieve speedups of three to six on realistic processors. 1 Stephen W. Melvin, Yale N. Patt |
ISCA | 1 |
| 1989 | Performance benefits of large execution atomic units in dynamically scheduled machinesabstractIn this paper we identify three types of atomic units, or indivisible units of work: architectural atomic units (defined by architecture level interrupts and exceptions), compiler atomic units (defined by compiler code generation) and execution atomic units (defined by run-time interruptibility). We discuss trade-offs for these units and show that size has different performance implications depending on the atomic unit. We simulate a number of different implementations of the VAX architecture, focusing on different execution atomic unit sizes. We show that significant performance benefits can be achieved by having large execution atomic units in dynamically scheduled machines. Stephen W. Melvin, Yale N. Patt |
ICS | 1 |
| 1988 | The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System KernelsabstractWe have developed a tool based on microcode modifications to a VAX 8600 which allows a wide variety of operating system measurements to be taken with minimal perturbation and without the need to modify any operating system software. A trace of interrupts, exceptions, system calls and context switches is generated as a side-effect to normal execution. In this paper we describe the tool we have developed and present some results we have gathered under both UNIX 4.3 BSD and VAX/VMS V4.5. We compare the process fork behavior of two different command shells under UNIX, look at context switch rates for interactive and batch workloads and generate a histogram for network interrupt service time. Stephen W. Melvin, Yale N. Patt |
SIGMETRICS | 1 |
| 1987 | Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer
Jeffrey D. Gee, Stephen W. Melvin, Yale N. Patt |
ICLP | 2 |