The problem of the incorporation of pattern features with unusual distributions is well known within pattern recognition systems even if not easily addressed. The problem is more acute when features are derived from characteristics of given integrated electronic circuits. The current paper introduces novel efficient techniques for normalising sets of features which are highly multi-modal in nature, so as to allow them to be incorporated within a single encryption key generation system based primarily on measured hardware characteristics. The utility of the proposed system lies in the observation that the need for data sent to and from remote network nodes to be secure and verified is substantial. Security can be improved by using encryption techniques based on keys, which are based on unique properties of the individual nodes within the network. This will serve both to minimize the need for key storage and sharing as well as to validate the initiator node of a message.

This research presents a test-bench implementation of a novel debug support system that targets the needs of hard real-time embedded systems. The solution provides over 70 percent combined program and data trace compression using a low complexity messaging framework and subtraction based differential compression. The test-bench is based on an open source multi-processor system-on-chip design, where novel debug support has been attached through defined interfaces and close integration of the debug adapter with the processor cores. Synthesis to an FPGA platform shows that the approach of using core adapters to implement debug support with a defined core generic interface is practical, and that the resulting circuitry is compact

On-chip program and data tracing is now an essential part of any system level development platform for system-on-chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each core's debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging network-on-chip architectures.