In the fourth industrial revolution, securing the protection of supply chains has become an ever-growing concern. One such cyber threat is a hardware Trojan (HT), a malicious modification to an IC. HTs are often identified during the hardware manufacturing process but should be removed earlier in the design process. Machine learning-based HT detection in gate-level netlists is an efficient approach to identifying HTs at the early stage. However, feature-based modeling has limitations in terms of discovering an appropriate set of HT features. We thus proposeNHTD-GLin this paper, a novel node-wise HT detection method based on graph learning (GL). Given the formal analysis of the HT features obtained from domain knowledge,NHTD-GLbridges the gap between graph representation learning and feature-based HT detection. The experimental results demonstrate thatNHTD-GLachieves 0.998 detection accuracy and 0.921 F1-score and outperforms state-of-the-art node-wise HT detection methods.NHTD-GLextracts HT features without heuristic feature engineering.

Graph neural networks (GNNs) have been actively employed in hardware security and have demonstrated remarkable performance. In particular, GNN models for hardware Trojan (HT) detection significantly outperform existing machine learning-based detection methods. However, GNNs have a potential vulnerability to membership inference attack (MIA), which aims to determine whether a given sample is used in the training dataset. In this paper, we investigate the threat of MIAs for GNN-based HT detection models. First, the MIA scheme for GNN-based HT detection models is established based on the basic MIA settings. The experimental results demonstrate that MIA for GNN-based HT detection can leak information about the HTs included in the training dataset with a 0.945 attack AUC score in the worst-case scenario. Based on this observation, we propose a defense method against MIA utilizing a domain generalization technique. The proposed defense method successfully mitigated the vulnerability of MIA and degraded the attack AUC score to 0.536 for the netlist level while maintaining the original HT detection performance.

In this study, we present an autonomous driving sys-tem that utilizes a binarized autoencoder implemented on a Field Programmable Gate Array (FPGA). The binarized autoencoder compresses the image into optimal features in this system. The recurrent neural network then determines the following control based on the feature values extracted from the autoencoder and the rotation speed of the motor. We reduced the model size by binarizing the autoencoder because of the limited on-chip memory of the FPGA. We implemented the system on an Ultra96-V2, a board with a programmable logic and processing system. The robot employing our implemented system exhibits robust control by recognizing the entire road marking and road edge line as a feature and drives autonomously along the specified route.

Recently, with the increase in outsourcing of IC design and manufacturing, the possibility of inserting hardware Trojans, which are circuits with malicious functions, has been pointed out. To prevent this threat, a method to identify hardware Trojans using neural networks has been proposed. On the other hand, adversarial attacks have emerged that modify circuit design information to reduce the accuracy of hardware-Trojan classification by neural networks. Since the features designed by existing methods do not take the attacks into account, it is necessary to consider a new method for countermeasures. In this paper, out of 76 features that are strongly related to hardware-Trojan features, we investigate them from the viewpoint of the robustness against the adversarial attacks on circuit design information and newly propose 24 hardware-Trojan features. We compare the classifiers using the proposed 24 features with the classifiers using 11, 36, 51, and 76 existing features, respectively and confirm that the proposed ones are more robust in identifying hardware Trojans in circuits subjected to the adversarial attacks.

This paper presents an autonomous driving system utilizing FPGA-based image processing. We develop a robot that our system is implemented on Ultra96-V2, a board with programmable logic and processing system. We use ROS, a middleware framework for developing robots, to manage the system such as controlling hardware devices, localization and determination of the direction to go. We implement a neural network to detect road markings on the road on a programmable logic on the board. The robot with our system implemented drives autonomously along the specified route on a miniature road, recognizing edge line and road markings.