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Yasumasa Tsukamoto

dblp:25/5303 · DBLP profile ↗
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6ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0002-0963-6940ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 1 heaviest of 1, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
process and device simulation
0.011995
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995

Methods — techniques the papers use, named apart from their topics

finite-difference numerical modeling · 0.0
YearPublicationVenuePosition
2018 A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Tanaka, Koji Nii
IEEE Trans. Very Large Scale Integr. Syst.2
2014 28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
abstract
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa
IEEE Trans. Very Large Scale Integr. Syst.6
2012 A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues
abstract
We discuss dynamic read and write stabilities of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. Test chips which include 1-Mbit single-port SRAM and 512-kbit dual-port SRAM macros are designed and fabricated. A Good correlation for minimum operating voltage (Vmin) between simulation and measurement is observed. We also introduce the test screening circuitry which takes the dynamic stability into consideration. We obtain the appropriate screening results from the evaluations of the testchip. It is also confirmed assured screening with 2.0% dynamic stability fault detection for an SoC product.
Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto
Asian Test Symposium2
2011 A dynamic body-biased SRAM with asymmetric halo implant MOSFETs
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii
ISLPED2
2005 Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability
abstract
6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.
Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
ICCAD1
1995 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion
abstract
This paper presents a three-dimensional (3-D) numerical surface diffusion model of BPSG glass flow of surface tension. The analysis region is divided into small cubic cells. Material surface is described as an equi-concentration (equi-existence rate) area which is obtained by linear interpolation between the cells. 3-D surface curvature is defined as the ratio of the increment of surface area to that of volume in a small interface area. Flux of flow is proportional to gradient of the surface curvature, and the direction is from positions of larger curvature to that of small curvature. The flow algorithm is that particles move from the mass-center of the equi-concentration area of a cell to that of the neighbor cells across the contact lines of the cell boundary and the equi-concentration area. This paper presents two 3-D simulations of flow which show that this model can be applied for not only cylindrical symmetry but also general 3-D topography. Also, the surface diffusion coefficient for the total concentration (C/sub imp/: P/sub 2/O/sub 5/ and B/sub 2/O/sub 3/) is derived using the model by fitting 2-D simulations to the experiments at 850/spl deg/C.>
Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6