Diagnostic march tests are powerful tests that are capable of detecting and identifying faults in memories. Although march SS was published for detecting simple static faults, no test has been published for identifying all faults possibly present in memory cells. In this paper, we target all published simple static faults. We identify faults that cannot be distinguished due to their analog behavior. We present a new methodology for generating irredundant diagnostic march tests for any desired subset of the simple static faults using the necessary and sufficient conditions for fault detection. Using that methodology, along with a verification tool, and trial and error, we were able to build a new diagnostic test for all distinguishable faults named march DSS. March DSS is the first test that is capable of identifying all distinguishable memory static faults. Compared to the latest most comprehensive published diagnostic march test, march DSS provides significant improvement in terms of fault coverage, time complexity, and power consumption. By targeting the same faults, we were able to provide a new test equivalent to the latest published test with 46% improvement in time complexity.

With the continued advances in miniaturization, bit-line (BL) coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of BL coupling on the faulty behavior of defective dynamic RAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a Spice simulation model. Two BL coupling mechanisms are identified (pre-sense and post-sense coupling), which are found to have a partly opposing effect on the faulty behavior. It is shown that BL coupling causes a special kind of coupling fault between adjacent memory cells. In addition, the influence of BL twisting on the faulty behavior of the memory is analyzed and simulated. The results indicate strong correspondence between theory and simulation and show the importance of Spice simulation as a vital tool for fault analysis

We show that no published march test detects all march-test detectable instances of linked faults in memories. We present necessary and sufficient conditions for detection of single cell linked faults. We identify the set of faults that are undetectable by march tests. We also present sets of faults that dominate all march-test detectable instances of linked multiple cell faults along with the necessary and sufficient conditions for their detection. Using a test generator that takes these conditions as input, we generate the first march tests that detect all march-test detectable linked faults. By considering the subsets of linked faults targeted by the well-known March A and March B tests, we also prove that these well-known tests are optimal for the corresponding sets of target faults.

A large number of march tests that provide different fault coverages have been published and a few methodologies have been presented for automatically generating march tests. This paper presents a new methodology for generating optimal and uniform march tests. The new methodology uses a compact representation of faults, generates necessary and sufficient conditions for their detection, and generates tests using the conditions along with the properties of march tests. The methodology is demonstrated as being more efficient than those previously presented. It has been used to (a) generate new optimal tests that are uniform, which are desired to simplify BIST architecture, (b) prove the optimally of some well-known tests such as March C-, and (c) generate a complete set of optimal march tests for different combinations of faults. The proposed approach hence provides memory manufacturers with an optimal test to cover the types of faults that are likely to occur in their memories.

While any efficient test developed for off-line testing of memory chips can be easily adapted for in-system testing of single level memory systems, no efficient methodology is known to transform such a test for in-system testing of multilevel memory systems that have one or more levels of cache. The main challenge is in transforming the known test to test the tags of the cache (testing of the data part of the cache is relatively straightforward). In this paper we present a general methodology to transform march tests for in-system testing of tags of direct mapped caches. The transformation has been used to obtain new versions of March B and March X tests. It is shown that the new versions of tests detect the same sets of faults in the cache tags as their original versions detect in memory chips. Finally, it is demonstrated that the proposed version of March B has significantly lower time complexity than previously proposed tests and can be applied without any modification of the memory system hardware.