A concept of mutual transportation by cooperative multiple mobile robots is proposed in this paper, which enables robots to process complicated or heavy-duty tasks, and overcome the large obstruction in an environment. A method of mutual transportation utilizing forklift mechanisms is introduced with discussion on the lifting process and moving process. Cooperative mobile robots including a holonomic omni-directional platform and a forklift mechanism are developed. Finally, as an example of applications of mutual transportation, step-climbing motion is presented, and the motion realized by the developed mobile robots is shown.

A shared radix 2 division and square root implementation using a self-timed circuit is presented. The same execution time for division and square root is achieved by using an on-the-fly digit decoding and a root multiple generation technique. Most of the hardware is shared, and only several multiplexers are required to exchange a divisor multiple and a root multiple. Moreover, quotient selection logic is accelerated by a new algorithm using a 3-b carry propagation adder. The implementation of the shared division and square root unit is realized by assuming 0.3 /spl mu/m CMOS technology. The wiring capacitance and other parasitic parameters are taken into account. The execution time of floating point 55-b full mantissa division and square root is expected to be less than 30 ns in the worst case of an input vector determined by an intensive circuit simulation.>

This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.

This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.

Semicustom and custom LSIs have become very important for system manufacturers because they provide system products with distinctive features that cannot be furnished by using only standard LSIs such as microprocessors. From this point of view, rapid development is essential for semicustom and custom LSIs, but there are other factors to be considered for determining the device technology and design methodology such as performance requirements, allowable development costs, and production quantities. In this paper, these aspects for semicustom and custom LSI development are discussed. We first review the device technology and then discuss various design methodologies with an emphasis on standard cell designs. New design methodologies, such as silicon compilers and AI approaches, are also included.