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Foad Dabiri

dblp:25/6676 · DBLP profile ↗
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15ranked-venue papers
4as first author
0since 2021 · last 2014
0009-0006-8794-4638ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 3 first-authorComputer networks · 3Software engineering, systems software and programming languages · 3 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 59% Hardware reliability and fault tolerance · 36% Energy-efficient computing · 5%
Theoretical computer science
1 paper
Graph algorithms and graph theory · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
gate sizing
0.112008
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Hardware reliability and fault tolerance › soft errors
single-event upset
0.112008
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Hardware reliability and fault tolerance
soft errors
0.112008
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
high-level synthesis
0.112006
Optimal register sharing for high-level synthesis of SSA form programs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › high-level synthesis › resource binding
register allocation
0.112006
Optimal register sharing for high-level synthesis of SSA form programs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › high-level synthesis
static single assignment form
0.112006
Optimal register sharing for high-level synthesis of SSA form programs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Energy-efficient computing › low-power design
power optimization
0.012008
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

linear scan register allocation · 0.1graph coloring · 0.1statistical modeling · 0.1nonlinear programming · 0.1convex programming · 0.1
YearPublicationVenuePosition
2014 Provably minimal energy using coordinated DVS and power gating
abstract
Both energy and execution speed can be greatly impacted by clock and power gating, nonlinear voltage scaling, and leakage energy. We address the problem of coordinated power gating and dynamic voltage scaling (DVS) to minimize the overall energy consumption of an application under user-specified timing constraints. We prove that a solution provided by our convex programming formulation that uses at most two versions of hardware, where each version uses its own constant voltages, is optimal. Comprehensive evaluation of the new approach demonstrates energy improvements over traditional DVS and DVS and power gating techniques by factors of 1.44X-2.97X and 1.44X-2.82X, respectively.
Nathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak
DATE3
2013 HERMES: Mobile system for instability analysis and balance assessment
abstract
We introduce Hermes , a lightweight smart shoe and its supporting infrastructure aimed at extending gait and instability analysis and human instability/balance monitoring outside of a laboratory environment. We aimed to create a scientific tool capable of high-level measures, by combining embedded sensing, signal processing and modeling techniques. Hermes monitors walking behavior and uses an instability assessment model to generate quantitative value with episodes of activity identified by physician, researchers or investigators as important. The underlying instability assessment model incorporates variability and correlation of features extracted during ambulation that have been identified by geriatric motion study experts as precursor to instability, balance abnormality and possible fall risk. Hermes provides a mobile, affordable and long-term instability analysis and detection system that is customizable to individual users, and is context-aware, with the capability of being guided by experts. Our experiments demonstrate the feasibility of our model and the complimentary role our system can play by providing long-term monitoring of patients outside a hospital or clinical setting at a reduced cost, with greater user convenience, compliance and inference capabilities that meet the physician's or investigator's needs.
Hyduke Noshadi, Foad Dabiri, Shaun Ahmadian, Navid Amini, Majid Sarrafzadeh
ACM Trans. Embed. Comput. Syst.2
2013 Behavior-oriented data resource management in medical sensing systems
abstract
Wearable sensing systems have recently enabled a variety of medical monitoring and diagnostic applications in wireless health. The need for multiple sensors and constant monitoring leads these systems to be power hungry and expensive with short operating lifetimes. We introduce a novel methodology that takes advantage of contextual and semantic properties in human behavior to enable efficient design and optimization of such systems from the data and information point of view. This, in turn, directly influences the wireless communication and local processing power consumption. We exploit intrinsic space and temporal correlations between sensor data while considering both user and system contextual behavior. Our goal is to select a small subset of sensors that accurately capture and/or predict all possible signals of a fully instrumented wearable sensing system. Our approach leverages novel modeling, partitioning, and behavioral optimization, which consists of signal characterization, segmentation and time shifting, mutual signal prediction, and a simultaneous minimization composed of subset sensor selection and opportunistic sampling. We demonstrate the effectiveness of the technique on an insole instrumented with 99 pressure sensors placed in each shoe, which cover the bottom of the entire foot, resulting in energy reduction of 72% to 97% for error rates of 5% to 17.5%.
Hyduke Noshadi, Foad Dabiri, Saro Meguerdichian, Miodrag Potkonjak, Majid Sarrafzadeh
ACM Trans. Sens. Networks2
2011 Joint consideration of energy-efficiency and coverage-preservation in microsensor networks
abstract
Abstract This paper presents an energy‐efficient and coverage‐preserving communication protocol which distributes a uniform energy load to the sensors in a wireless microsensor network. This protocol, called Distance‐based Segmentation (DBS), is a cluster‐based protocol that divides the entire network into equal‐area segments and applies different clustering policies to each segment to (1) reduce total energy dissipation and (2) balance the energy load among the sensors. Therefore, it prolongs the lifetime of the network and improves the sensing coverage. Moreover, the proposed routing protocol does not need any centralized support from a certain node which is at odds with aiming to establish a scalable communication protocol. Results from extensive simulations on two different network configurations show that by lowering the number of wasteful transmissions in the network, the DBS can achieve as much as a 20% reduction in total dissipated energy as compared with current cluster‐based protocols. In addition, this protocol is able to distribute energy load more evenly among the sensors in the network. Hence, it yields up to a 66% increase in the useful network lifetime. According to the simulation results, the sensing coverage degradation of the DBS is considerably slower than that of the other cluster‐based protocols. Copyright © 2009 John Wiley & Sons, Ltd.
Navid Amini, Alireza Vahdatpour, Foad Dabiri, Hyduke Noshadi, Majid Sarrafzadeh
Wirel. Commun. Mob. Comput.3
2009 Hardware aging-based software metering
abstract
Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property and digital rights management. We have developed the first HSCM technique that employs intrinsic aging properties of components in modern and pending integrated circuits (ICs) to create the first self-enforceable HSCM approach. There are variety of hardware aging techniques that range from electro-migration in wires to slow-down of crystal-based clocks. We focus on transistor aging due to negative bias temperature instability (NBTI) effects where the delay of gates increases proportionally to usage times. We address the problem of how we can measure the amount of time a particular licensed software (LS) is used by designing an aging circuitry and exposing it to the unique inputs associated with each LS. If a particular LS is used longer than specified, it automatically disables itself. Our novel HSCM technique uses a multi-stage optimization problem of computing the delays of gates, their aging degradation factors, and finally LS usage using convex programming. The experimental results show not just viability of the technique but also surprisingly high accuracy in the presence of measurement noise and imperfect aging models. HSCM can be used for many other business and engineering applications such as power minimization, software evaluation, and processor design.
Foad Dabiri, Miodrag Potkonjak
DATE1
2009 Energy minimization for real-time systems with non-convex and discrete operation modes
abstract
We present an optimal methodology for dynamic voltage scheduling problem in the presence of realistic assumption such as leakage-power and intra-task overheads. Our contribution is an optimal algorithm for energy minimization that concurrently assumes the presence of (1) non-convex energy-speed models as opposed to previously studied convex models, (2) discrete set of operational modes (voltages) and (3) intra-task energy and delay overhead. We tested our algorithm on MediaBench and task sets used in previous papers. Our simulation results show an average of 22% improvement in energy reduction in comparison with optimal algorithms for convex models without switching overhead and on average of 24% with consideration for energy and delay overheads. This analysis lays the groundwork for improving functionality in CAD design through non-convex techniques for discrete models.
Foad Dabiri, Alireza Vahdatpour, Miodrag Potkonjak, Majid Sarrafzadeh
DATE1
2009 An efficient placement and routing technique for fault-tolerant distributed embedded computing
abstract
This article presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. The driver application that we present is a medical jacket, which requires an extremely high level of robustness and fault tolerance. The power consumption of such jacket is another key technological constraint. Our proposed interconnection network is a mesh of wires. A jacket made of fabric and wires would be susceptible to accidental damage via tears. By modeling the tears, we evaluate the probability of having failures on every segment of wires in our mesh interconnection network. Then, we study two problems of placement and routing in the sensor networks such that the fault tolerance is maximized while the power consumption is minimized. We develop efficient integer linear programming (ILP) formulations to address these problems and perform both placement and routing, simultaneously. This ensures that the solution is a lower bound for both problems. We evaluate the effectiveness of our proposed techniques on a variety of benchmarks.
Roozbeh Jafari, Hassan Ghasemzadeh 0001, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh
ACM Trans. Embed. Comput. Syst.3
2009 A Telehealth Architecture for Networked Embedded Systems: A Case Study in In Vivo Health Monitoring
abstract
The improvement in processor performance through continuous breakthroughs in transistor technology has resulted in the proliferation of lightweight embedded systems. Advances in wireless technology and embedded systems have enabled remote healthcare and telemedicine. While medical examinations could previously extract only localized symptoms through snapshots, now continuous monitoring can discretely analyze how a patient's lifestyle affects his/her physiological conditions and if additional symptoms occur under various stimuli. We demonstrate how medical applications in particular benefit from a hierarchical networking scheme that will improve the quantity and quality of ubiquitous data collection. Our Telehealth networking infrastructure provides flexibility in terms of functionality and the type of applications that it supports. We specifically present a case study that demonstrates the effectiveness of our networked embedded infrastructure in an in vivo pressure application. Experimental results of the in vivo system demonstrate how it can wirelessly transmit pressure readings measuring from 0 to 1.5 lbf/in (2) with an accuracy of 0.02 lbf/in (2). The challenges in biocompatible packaging, transducer drift, power management, and in vivo signal transmission are also discussed. This research brings researchers a step closer to continuous, real-time systemic monitoring that will allow one to analyze the dynamic human physiology.
Foad Dabiri, Tammara Massey, Hyduke Noshadi, Hagop Hagopian, C. K. Lin, Robert Tan, Jacob Schmidt, Majid Sarrafzadeh
IEEE Trans. Inf. Technol. Biomed.1
2008 Theoretical Bound and Practical Analysis of Connected Dominating Set in Ad Hoc and Sensor Networks
Alireza Vahdatpour, Foad Dabiri, Maryam Moazeni, Majid Sarrafzadeh
DISC2
2008 General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
abstract
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event upsets (SEUs) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a nonlinear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit. We prove that it is sufficient to consider a linear number of constraints. 4) We generalize our methodology to include nonlinear delay models and leakage power as well. As an important preprocessing step, we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. Furthermore, we adapt our method to incorporate process variation and evaluate our gate sizing technique under uncertainty. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100%-200% while, on average, the power reduction is simultaneously decreased by less than 6%-10%, respectively, compared to the optimal power saving with no error rate constraints.
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2007 Localization Using Low-Resolution Optical Sensors
abstract
In wireless sensor networks, the data collected from numerous low end sensors can be equivalent or superior to a few high fidelity sensors. In this paper, we evaluate the validity of this concept with low-resolution optical sensors. We implemented passive localization using visual object identification techniques on a field programmable gate array (FPGA) sensor platform. The complexity, memory utilization, and accuracy of our algorithms were analyzed for performance on a resource constrained environment. We show that low-resolution optical sensors can accurately localize objects on a global two dimensional plane. We also present a model that quantifies fidelity versus scale for optical sensors. Using our model and application, we demonstrate that low-fidelity optical sensors are an effective tool in sensor networks and at a certain scale can provide superior coverage of an area over a high-resolution camera. This analysis lays the groundwork for future advances in optical sensors.
Tammara Massey, Rahul Kapur, Foad Dabiri, Linh Nam Vu, Majid Sarrafzadeh
MASS3
2006 Low power light-weight embedded systems
abstract
Light-weight embedded systems are now gaining more popularity due to the recent technological advances in fabrication that have resulted in more powerful tiny processors with greater communication capabilities that pose various scientific challenges for researchers. Perhaps the most significant challenge is the energy consumption concern and reliability, mainly due to the small size of batteries. In this tutorial, we portray a brief description of low-power, light-weight embedded systems, depict several power profiling studies previously conducted, and present several research challenges that require low-power consumption in embedded systems. For each challenge, we highlight how low-power designs may enhance the overall performance of the system. Finally, we present a several techniques that minimize the power consumption in such systems.
Majid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Tammara Massey, Ani Nahapetian
ISLPED2
2006 Optimal register sharing for high-level synthesis of SSA form programs
abstract
Register sharing for high-level synthesis of programs represented in static single assignment (SSA) form is proven to have a polynomial-time solution. Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|V|+|E|) time algorithm. Chordal graph coloring reduces the number of registers allocated to the program by as much as 86% and 64.93% on average compared to linear scan register allocation.
Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2005 Wireless Sensor Networks for Health Monitoring
abstract
We propose a platform for health monitoring using wireless sensor networks. Our platform is a new architecture called CustoMed that will reduce the customization and reconfiguration time for medical systems that use reconfigurable embedded systems. This architecture is a network enabled system that supports various wearable sensors and contains on-board general computing capabilities for executing individually tailored event detection, alerts, and network communication with various medical informatics services. The customization of such system with a large number of "med nodes" is extremely fast even by non-engineering staff. In this paper, we present the architecture of such device along with experimental analysis that evaluates the performance of such system.
Roozbeh Jafari, Andre Encarnacao, Azad Zahoory, Foad Dabiri, Hyduke Noshadi, Majid Sarrafzadeh
MobiQuitous4
2005 An Efficient Placement and Routing Technique for Fault-Tolerant Distributed Embedded Computing
abstract
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. The driver application that we present is a medical jacket which requires an extremely high level of robustness and fault tolerance. The power consumption of such jacket is another key technological constraint. Our proposed interconnection network is a mesh of wires. A jacket made of fabric and wires would be susceptible to accidental damage via tears. By modeling the tears, we evaluate the probability of having failures on every segment of wires in our mesh interconnection network. Then we study two problems of placement and routing in the sensor networks such that the fault tolerance is maximized while the power consumption is minimized. We develop efficient integer linear programming (ILP) formulations to address these problems and perform both placement and routing simultaneously. This ensures that the solution is a lower bound for both problems. We evaluate the effectiveness of our proposed techniques on a variety of benchmarks.
Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh
RTCSA2