Demo Data from EDBT 2026 / reviewers in the wild / expert
Xiaoyin Yao
dblp:25/8314
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 50% Integrated circuit design · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › random-access memory
SRAM |
0.1 | 1 | 2010 | In-situ characterization and extraction of SRAM variability · DAC 2010 |
Integrated circuit design › memory circuit design
SRAM cell design |
0.1 | 1 | 2010 | In-situ characterization and extraction of SRAM variability · DAC 2010 |
Methods — techniques the papers use, named apart from their topics
single-ended test procedure · 0.1non-iterative decomposition · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | In-situ characterization and extraction of SRAM variabilityabstractMeasurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is < 4% at all corners. Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen 0024, Yu Cao 0001, Lawrence T. Clark |
DAC | 3 |