The increasing reliance on third-party intellectual property (IP) cores in modern integrated circuit (IC) design has introduced significant security vulnerabilities, particularly the risk of Hardware Trojans (HTs). These malicious modifications can compromise system integrity, leading to data leakage, unauthorized access, or functional failures. Traditional detection methods often depend on the availability of a golden chip, which is not always feasible. This paper presents the 2025 ICCAD CAD Contest Problem A, which challenges participants to develop machine learning-based solutions for detecting HTs directly from gate-level netlists without requiring a golden reference. The problem is formulated with defined Trojan behaviors, input/output specifications, and evaluation metrics, including correctness and F1 score. The contest aims to foster innovation in HT detection by leveraging advanced data-driven techniques and scalable analysis frameworks.

Traditionally, logic synthesis/optimization metric would be majorly determined by PPA (power, performance, area). However, as the technology node shrinks and the design process becomes extremely complicated, iterative optimization flow and local re-synthesis might be invoked to optimize for more variant purposes. It is necessary to have a methodology which is not just a simple cost-function-based algorithm but also can optimize and legalize a design according to a more complex cost estimator.

Boolean Matching problem determines whether two Boolean functions are functionally equivalent under the permutation and negation of inputs and outputs. Prior contest [1] has extended the problem to allow inputs binding with constant value and the ports matching can be one-to-many projection. In this contest, we further extended the problem to consider the ports grouping information, which is caused by the buses or datapaths in the modern digital IC design.

Extracting circuit functionality from a gate-level netlist is critical in CAD tools. For security, it helps designers to detect hardware Trojans or malicious design changes in the netlist with third-party resources such as fabrication services and soft/hard IP cores. For verification, it can reduce the complexity and effort of keeping design information in aggressive optimization strategies adopted by synthesis tools. For Engineering Change Order (ECO), it can keep the designer from locating the ECO gate in a sea of bit-level gates.

In this letter, we predict the locations as probability distributions for the tasks of image object detection. We adopt the Kullback-Leibler divergences as the regression losses to train the deep neural networks. Since most existing evaluations label the objects with rectangular bounding boxes, we propose the Nearest Distribution Converter to find the closest uniform distributions from the predicted ones. Our proposed method can improve the detected accuracy measured in mAP by 0.57%, 0.75%, and 0.48% on the models YOLOv3, the YOLOv4-tiny, and the YOLOv4, respectively.

Functional ECO is an essential solution in the VLSI design flow. The technique is to realize the functional changes with a minimal patch netlist in the gate-level netlist. As the increasing of the design complexity, functional ECO becomes more and more difficult to generate a minimal patch. ICCAD 2021 CAD contest calls for a feasible and efficient ECO algorithm with behavioral change guidance. More than ordinary functional ECO problems, the RTL designs are provided. Contestants can utilize the behavioral change in RTL designs to minimize the patch for G1.

Equivalence checking is the practical industrial solution to sign-off digital functionality for large-scale circuits. However, when design contains implicit and explicit X-values, the complexity of equivalence checking increases and heuristics used in binary-value equivalence checking may not be applicable for X-value equivalence checking. The goal of the ICCAD 2020 CAD contest is to ask the good algorithm and heuristic to solve the X-value equivalence checking. In this contest, we provide the benchmark suites for contestant to evaluate their program. We hope the contest result can improve industry applications and bring more research interests.

Using sampling patterns is always a powerful method to save efforts for the problems with large input space since it can quickly help identify cases' properties. The meaning behind these sampling results can be informative and useful, but these results may be unreadable to humans. Therefore, in 2019 CAD Contest [1], we formulate a problem of “logic regression on high dimensional Boolean space”. Given a blackboxed input-output relation generator, contestants are required to find a minimal Boolean logic circuit which matches the input-output relations of the given generator. In this contest, we provide benchmarks that address industrial applications of logic regression with several scenarios and different scales of input space to evaluate contestants' algorithms. We expect that the contest results can help industrial application and attract interesting academic research.

With a functional Engineering Change Order (ECO) problem, the quality of patch plays an important role in the performance of the patched circuit. In this contest, contestants need to generate patch functions that will make two circuits equivalent, while minimizing the resource cost of the generated patches. Resource cost is the comprehensive physical cost of all the patches, and minimizing the resource cost implies improving patch quality (timing, power, routing, or area). The resource cost of patches can be modeled as a weighting function with respect to several physical properties of nodes used for patches. In ICCAD 2017 CAD Contest, we have assigned each internal node a reasonable constant weight to represent the corresponding physical cost if the node is used for generating patches. Also, the resource cost of the patches is calculated as the weight summation of patches' support nodes. This formulation can elegantly identify wanted algorithms for the resource-aware patch generation problem.

Boolean Matching is significant to industry applications, such as library binding, synthesis, engineer change order, and hardware Trojan detection. Instead of basic Boolean matching, Non-exact Projective NPNP Boolean Matching allows to match two designs by not only negating and permuting inputs/outputs but also merging them or binding constants to inputs. Besides, the matching goal is extended to achieve the largest number of output equivalences between two designs. This kind of Boolean matching may get better quality in the related applications due to more flexibility and scalability, and the development of its algorithms is more challengeable. Hence, this problem has some research values. In ICCAD 2016 CAD contest, given two designs, participants need to decide how to permute, negate and merge designs' inputs/outputs or bind constants for achieving largest number of output equivalences. The score will be evaluated by how many outputs are equivalent and the runtime. We expect the contest result can improve industry applications and bring more research interests.

Equivalence checking (EC) and functional Engineering Change Order (ECO) on large-scale designs becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in how to partition the large-scale problems into smaller EC and ECO problem with lower complexity. In this contest, we ask the participants to design the algorithm to insert the corresponding cuts as the partitioned points on given two designs as simplifying the EC and ECO problems. The team correctly simplifying the problem most wins the contest. The benchmark suites are extracted from the real designs in our interesting applications. We look forward to triggering the academic area to investigate on this problem.

Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular applications. From practical experience, the run time yielded by solving SAT problems using the default setting is far from best run time; same is true for CNF encoding. In this contest, we ask the participants to design the algorithm for exploring the best setting based on some sample cases, and we determine the contest winners by evaluating the run time for solving the remaining problems. The benchmark suites are extracted from the real designs in our applications of interest. We look forward to triggering the academic area in further investigating this problem.

As technology advances, there is an increasing need in the industrial domain for an algorithm that can map macro blocks. This type of algorithm would solve several front-end problems. For example, existing structural or functional algorithms cannot solve the challenge of mapping large-scale functions without boundary information. Fortunately, in practical problems, we only consider the target mapping functions that are the constructs of the datapath, and these macro blocks are easily recognized through their special arithmetic signatures. In this problem, the contestants need to design a mapping algorithm that recognizes macro blocks and replaces the mapped region with the macro blocks. Therefore, we can fairly evaluate the quality of the mapping algorithm as the size reduction of the revised netlist. Under our well-designed benchmarks, we will clearly differentiate the capability of proposed algorithms with several indexes. We look forward to triggering the academic area to investigate on this problem.

In modern SoC design flow, verification and validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in verification and validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW verification and validation flow.

In this paper, we proposed a novel interpolant generation algorithm without constructing the resolution graph of the unsatisfiability proof. Our algorithm generates the interpolant by building sub-interpolants from conflict analyses and then merges them based on the last decision conflict. The experimental results show that our algorithm has the advantages over the prior interpolant generation techniques in both memory usage and interpolation circuit size.