This paper presents the design of a 128 GS/s 64x time-interleaved SAR ADC, featuring an ultra-wideband two-rank hierarchical track-and-hold architecture maintaining 62 GHz bandwidth in 22nm CMOS FD-SOI technology. To achieve both, high bandwidth and concurrently adequate sampling linearity, an inductively peaked input network and first-stage source follower with pseudo-differential gain coupling is used, taking advantage of a dual -0.5V and 0.9V power supply. The front-end T/H also utilizes a mix of static and dynamic body-biasing techniques enabled by the 22nm CMOS SOI technology to further improve the linearity and signal gain. Each second-level buffer drives four 6-bit asynchronous loop-unrolled SAR ADCs at a conversion rate of 2 GS/s, using speed-optimized dynamic logic cells and MDAC redundancy to fulfil the sampling speed requirements. Time-interleaving mismatch effects such as gain, offset and sample skew errors are calibrated off-chip. The total signal bandwidth across the input network, first-level buffer and T/H stage exceeds 62.2/53.9 GHz and the ADC achieves a SNDR of well above 35.5/32.3 dB up to 19.7 GHz as well as 31.7/28.6 dB up to Nyquist-frequency in TT/SS corner.

In this article, an overview of the most recent fully-depleted silicon on insulator technology (FD-SOI) design techniques in the field of mixed-signal circuits and systems are given. Cutting edge performance is achieved by using dynamic as well as static body-biasing techniques. 22FDX®is a 22nm CMOS FD-SOI technology providing both, a unique wide-band body-bias tuning range in conjunction with minimized parasitic device loads, due to the significant reduced pn junctions in the signal path. As a result, transistor transit frequencies exceeding 400GHz with improved linearity is achieved. With a linear threshold voltage sensitivity of around 75mV per Volt, 22FDX®gives designers a competitive additional degree of freedom. After introducing 22FDX®, a 5-bit 18.5GS/s flash ADC is presented utilizing body-biasing to generate accurate threshold voltage offsets within the comparators and thus omitting a power-hungry resistive ladder. Then, dynamic body-biasing is used for a 1.5GS/s track-and-hold circuit to improve the bandwidth while the leakage is reduced obtaining 80dBc SFDR up to the fourth Nyquist zone. Furthermore, a 26GHz ring oscillator is presented, which utilize the strong threshold voltage sensitivity to fully compensate corner dependency. Finally, a body-biasing controlled DAC linearization technique for multi-bit Sigma-Delta modulators enabling 90dBc SFDR, as well as a DAC driver termination impedance control for a 6GS/s 10-bit automotive Ethernet SST-DAC-Driver are presented.

This paper presents a flash ADC architecture employing a comparator well-body biasing technique to eliminate the classical differential-difference amplifier (DDA) as well as the power-hungry reference ladder to enable significant power savings. DDAs require two differential pairs, one for the actual input signal and the other for the reference voltage whereas the proposed comparator technique merely uses a single differential pair for the input signal reducing the power consumption of the power-hungry preamplifier by approx. 50%. Furthermore, the flash ADC reference levels of the presented flash ADC, are generated by altering the input transistor threshold voltages. The adopted 22nm FD-SOI technology provides a threshold voltage tuning gain of approx. 85mV/V. Using a 3V capacitive charge-pump, a nominal full-scale range of 500 mVppdis achieved. This way, the proposed method also eliminates comparator kickback and therewith the low impedance requirement to guarantee settling of the reference ladder. The adopted technology provides a strong isolation from the gate to the back-gate of the input devices. The proposed techniques are adopted in a 5-bit 18.5 GS/s flash ADC. The track-and-hold along with the isolating front-end input buffer provides 28 GHz input bandwidth. The front-end buffer and SC charge pump operate from a 1.5V power supply while all other building blocks (comparator and clock tree) operate from a 0.9V power supply. The total power consumption is 140mW including clock buffers. The ADC achieves a SNDR and SFDR of 31dB and 43 dBc and 28.5dB and 40 dBc respectively at low and Nyquist input frequencies.

This paper presents an approach to optimally place noise coupling transfer functions (NCFs) zeros across the passband using oversampled analog-to-digital converters (ADCs). In addition, the presented optimization method is extended to account for and ultimately compensate NCF coefficient mismatch effects just using a single parameter only. As a result, NCF coefficient matching requirements are significantly relaxed enabling the robust design of accurate wideband oversampled data converters. The proposed technique is applied to two different ΣΔ ADCs both incorporating a second-order NCFs. For both ADCs, the optimal NCF zero placement is analytically calculated and verified through simulations. NCF coefficient mismatch simulations with the proposed single parameter compensation enabled, reveal a relaxed NCF coefficient matching requirement by a factor of 4× with only minor quantization noise penalties. Hence, the (analog) NCF filter area largely shrinks in size enabling ultra-compact oversampled ADCs.

This paper provides a new approach for emulating electric vehicle (EV) braking performance on a motor/dynamometer test bench. The brake force distribution between regenerative braking and friction braking of both the front and rear axles are discussed in detail. A brake controller is designed, which represents a very close model of an actual EV braking system and takes into account both regenerative and friction braking limitations. The proposed brake controller is then integrated into the existing controller of an EV Hardware-in-the-Loop (HIL) test bench, and its performance is validated in real-time using the same experimental setup.

We present a method for global estimation of joint velocities in robot manipulators. A non-minimal model of a robotic manipulator is used to design an adaptive observer capable of handling uncertainties in robot dynamics. Dimension of the proposed observer is shown to be at least 3n where n stands for the manipulator degrees of freedom. This number is less than the dimension of most of existing globally convergent adaptive observers. Global asymptotic convergence of system state estimates to their true values is achieved under no persistency of excitation condition. Smoothness of the dynamics of the proposed observer allows its easy implementation in comparison with non-smooth observers. Simulation results illustrate low noise sensitivity of the proposed observer in comparison with non-smooth observers.