In this paper we propose P4-based Atomic Multicast (P4mCast), a new in-network atomic multicast protocol to support total order guarantees for State Machine Replication (SMR) in cloud-based fault-tolerant and distributed applications. P4mCast builds on in-network computing, applying leader-based consensus to groups of prominent${P 4}$programmable switches in modern data center networks. P4mCast achieves significantly lower latency overhead in the microseconds scale while increasing the throughput one order of magnitude higher compared to state of the art software-based solutions.

The P4 community has recently put significant effort to increase the diversity of targets on which P4 programs can be implemented. These include fixed function and programmable ASICs, FPGAs, NICs, and CPUs. However, P4 programs are written according to the set of functionalities supported by the target for which they are compiled. For instance, a P4 program targeting a programmable ASIC cannot be extended with user-defined processing modules, which limits the flexibility and the abstraction of P4 programs. To address these shortcomings, we propose a heterogeneous P4 programmable data plane comprised of different targets that together appear as a single logical unit. The proposed data plane broadens the range of functionalities available to P4 programmers by combining the strength of each target. We demonstrate the feasibility of the proposed P4 data plane by coupling an FPGA with a soft switch which emulates a programmable ASIC. The proposed data plane is demonstrated with the implementation of a simplified L2 switch. The emulated ASIC match-table capacity is extended by the FPGA by an order of magnitude.The FPGA also integrates a proprietary module using a P4 extern.

Data center applications require strict characteristics regarding packet loss, fairness, head-of-line blocking, latency, and low processing overhead. Motivated by the emergence of IEEE Data Center Bridging, we explore the possibility of controlling congestion in Ethernet layer while guaranteeing those requirements. We propose HetFlow (Heterogeneous Flow) as a delay-based congestion control mechanism that controls & prevents congestion while achieving minimum queue length, minimum network latency, and high link utilization. HetFlow guarantees fairness between flows with different packet sizes and different round-trip times (RTTs). The results obtained through prototype and simulations show that HetFlow succeeded in preventing congestion and achieving low queue length, high link utilization, and fairness between flows.

In this paper, we introduce PFPSim, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures. The simulation model is automatically generated from a high-level description of the hardware/software architecture of the forwarding device and the behavioral description of the various modules in the architecture. Our high-level architectural description language is capable of defining many-core network processors as well as reconfigurable pipelines. The behavior of the fixed-function processing elements in the architecture is defined in C++. The code targeted for the processor cores, or reconfigurable pipeline stages, is compiled from P4, an emerging programming language for packet processing applications. Application developers can use PFPSim as a virtual prototype to simulate and debug their applications before hardware availability. Moreover, forwarding device architects can use PFPSim to evaluate the trade-offs between different hardware/software design decisions.

The increasing complexity of cyber-attacks necessitates the design of more efficient hardware architectures for real-time Intrusion Detection Systems (IDSs). String matching is the main performance-demanding component of an IDS. An effective technique to design high-performance string matching engines is to partition the target set of strings into multiple subgroups and to use a parallel string matching hardware unit for each subgroup. This paper introduces a novel pattern grouping algorithm for heterogeneous bit-split string matching architectures. The proposed algorithm presents a reliable method to estimate the correlation between strings. The correlation factors are then used to find a preferred group for each string in a seed growing approach. Experimental results demonstrate that the proposed algorithm achieves an average of 41% reduction in memory consumption compared to the best existing approach found in the literature, while offering orders of magnitude faster execution time compared to an exhaustive search.

Switch fabric in routers requires very tight characteristics in term of packet loss, fairness in bandwidth allocation, no head-of-line blocking and low latency. Such attributes are traditionally resolved using specialized and expensive switch devices. Motivated by the emergence of IEEE Data Center Bridging, we explore the possibility of using commodity Ethernet switches to achieve scalable, flexible, and more cost efficient solutions, while still guaranteeing the switch characteristics. In this context, we propose Ethernet Congestion Control & Prevention (ECCP), a novel concept to control and prevent congestion in switch fabrics. ECCP consists of (1) a method to estimate the available bandwidth along a given network path using a train of probes and (2) a rate control algorithm to adjust the sending rate of traffic along this path based on the estimated bandwidth. To prove ECCP and evaluate its characteristics, we present a first prototype based on the OMNEST simulator and conduct extensive experiments. Our analysis confirms that ECCP is a viable solution to (1) avoid congestion within the fabric, thus minimizing path latency and avoiding packet loss, (2) guarantee fair share of the link capacity between flows, and (3) avoid head of line blocking.