Audio communication on the public Internet suffers from not synchronized word clocks of the involved audio devices.The resulting clock drift leads to audio dropouts, which is typically compensated by a sample rate conversion (SRC) in standard telecommunication systems.This, however, does not fulfill the requirements of a high-quality audio system, in which all devices share one and the same word clock.Professional IP based network audio systems such as DANTE or AVB with their respective clock synchronization techniques have so been limited to LAN usage, where network jitter and loss have negligible importance regarding the required accuracy in the dimension of several nanoseconds.In a WAN, however, jitter in the millisecond dimension would lead to unacceptable measurement errors for the intended clock synchronization.As a consequence, we decided to investigate alternative clock synchronization techniques for WAN-distributed devices and developed a GNSS-based approach, which leads to precise clock synchronization.

In this paper, we present a bandwidth efficient retransmission method employing selective retransmission approach at a modulation layer under orthogonal frequency division multiplexing (OFDM) signaling. The proposed cross-layer design embeds a selective retransmission sub-layer in physical layer (PHY) that targets the retransmission of information symbols transmitted over poor quality OFDM sub-carriers. Most of the times, a few errors in decoded bit stream result in packet failure at medium access control (MAC) layer. The unnecessary retransmission of good quality information symbols of a failed packet has detrimental effect on the overall throughput of transceiver. We propose a cross-layer Chase combining with selective retransmission (CCSR) method by blending Chase combining approach at MAC layer and selective retransmission in PHY. The selective retransmission in PHY targets the poor quality information symbols prior to decoding, which results in lower hybrid automatic repeat reQuest retransmissions at MAC layer. We also present bit-error rate upper bound and throughput lower bound for the CCSR method. In order to maximize the throughput, we formulate optimization problem with respect to the amount of information to be retransmitted in selective retransmission. We also present an impact of selective retransmission on latency. The proposed CCSR method achieves a significant throughput gain as compared with the conventional Chase combining method.

In this study, the authors present a novel method to improve the performance of automatic repeat request (ARQ) protocol for multiple‐input–multiple‐output systems that use orthogonal frequency division multiplexing signalling by incorporating partial ARQ (PARQ) mechanism. As a typical ARQ frame has few number of errors, it is useful to retransmit partial sequence of symbols and recover from errors by consuming relatively low bandwidth. The observations from the first transmission and subsequent retransmission are used for joint detection. As a direct consequence of partial retransmission, the bandwidth and power efficiency of the overall system is improved considerably without substantial decrease in the performance. They achieve further bandwidth saving by omitting pilot sequence from the partial retransmission and acquire channel estimate in semi‐blind fashion. Partial retransmission of the original information symbol sequence allows the authors to formulate second‐order statistics based joint blind channel estimation problem by combining observations from two transmissions. Channel estimation ambiguity inherent to blind methods is resolved by combining cost functions of blind detection and least‐square estimator. To evaluate efficacy of the proposed PARQ method, they compare throughput of chase‐type hybrid‐ARQ and the proposed PARQ methods.

A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.