This work exploits Colored-Petri-Nets (CPN) for the early reliability estimation of hardware accelerators, significantly reducing the complexity during early design stages aimed at safety-critical systems. Our method builds high-level models of complex hardware accelerators to estimate reliability, integrating circuit characterization and fine-grain fault simulations on fundamental structures. We evaluate our methodology using six architecture variants of an on-chip hardware accelerator for deep learning (GPUs’ Tensor Cores). The results demonstrate that our approach reduces evaluation costs by 118x, achieving accuracy levels of up to 93.5% compared to exhaustive RT-level fault injection campaigns, while enhancing engineering productivity for early-stage designs.

One of the biggest concerns of Automotive System-on-Chip (SoC) design is the strict safety requirements for their hazardous operative scenarios. Commonly, designers employ Safety Mechanisms (SMs) to mitigate the fault effects and improve the SoC's safety levels. During the development phases, metrics, such as the Fault coverage (FC), are used to validate the effectiveness of the SMs. However, achieving such metrics, as defined by automotive standards, demands additional verification steps, resorting to extensive Fault Injection (FI) campaigns. These usually require mature design stages (e.g., RT-Gate level) involving significant simulation times and several iterations until obtaining the desired FC. Therefore, there is a high demand for new methodologies enabling FC estimation, supporting early-stage exploration, and avoiding expensive redesign phases. This work proposes a methodology exploiting Colored Generalized Stochastic Petri Nets (CGSPN) to model the SoC's architecture at a high level for FC estimation. The method optimizes and reduces the FI campaigns and is intended as a powerful tool supporting the development cycles of SMs, e.g., Software Test Libraries (STLs). Our experiments on an automotive test case indicate that STLs can be validated at a high level with minimal accuracy loss (1.1% on average) by optimizing the fault list in 28%. The results also showed a meaningful speedup of up to 160x in the development process of STLs.

Safety-critical systems can cause catastrophic effects when particular failures occur during their operation. These systems, used in diverse domains, including automotive SoCs, incorporate Safety Mechanisms (SMs) to enhance their safety performance and meet certification standards (e.g., ISO26262). A critical measure of safety performance is the Diagnostic Coverage (DC) of SMs, determined through extensive and expensive Gate-Level Fault Injection (FI) campaigns, as recommended by ISO26262. To address this challenge, designers need early DC estimation methods to efficiently develop more reliable SMs by reducing simulation times, redesign stages, and computational resources. Our previous work proposed an interactive simulation framework based on Colored Generalized Stochastic Petri Nets (CGSPN) for Fault Coverage (FC) estimation. This work incorporates the requirements of automotive safety standards to predict the efficiency of SMs. We propose a methodology for early-stage estimation of the DC, enabling efficient SM development and its Design Space Exploration (DSE), and the discovery of Failure Modes through CGSPN simulations. To the best of our knowledge, the proposed work is the first DC estimation approach based on high-level models such as CGSPN. The methodology was verified in an automotive SoC, showing an average estimation accuracy of 97.2% and a 175x speed-up for a Software Test Library (STL) compared to results obtained through an exhaustive RTL FI campaign.

The requirements of ISO26262 for the development of safety-critical Integrated Circuits (IC) demand substantial efforts on fault analysis for safety metrics evaluation. Failing to achieve the required conditions entails modifications to the circuit, additional iterations through critical design phases, and consequently extra costs and delays. For that reason, providing accurate methods to estimate safety metrics is of great importance. This paper proposes a methodology that can efficiently and precisely estimate the safety metrics of Automotive designs. The technique is based on the characterization of a netlist to determine how hardware components contribute to fault propagation. Also, by examining the test stimuli applied during simulation, we can rank Workloads/Testbenches according to their fault detection coverage. The approach was verified running fault injection campaigns on distinct gate-level hardware designs, including an Automotive CPU. Our results show that the fault detection coverage can be estimated with an average error rate of 3% at up to 20X faster execution times when compared to the traditional campaigns. Hence the methodology provides an efficient and cost-effective mechanism to support engineers in a confident design space exploration.

The current demands for developing safe automotive applications require extensive analysis and evaluation of potential random hardware faults. In general, part of this analysis is manually performed by experts, resulting in an expensive, time-consuming, and error-prone process. This paper proposes an automated approach to classify faults overlooked by traditional methods. Our methodology deploys code coverage and formal to identify nodes that do not disrupt safety-critical functionalities, enabling the classification of additional faults. The approach is validated based on an Automotive CPU, according to ISO 26262 guidelines. The results show an improvement in Diagnostic Coverage of 1.15%, increasing the Single Point Fault Metric (SPFM) to 97.3%, enabling ASIL C compliance without any hardware redundancy.

The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

The development of Integrated Circuits for the Automotive sector imposes on complex challenges. ISO26262 Functional Safety requirements entail extensive Fault Injection campaigns and complex analysis for the evaluation of deployed Software Tools. This paper proposes a methodology to improve Fault Analysis Tools Confidence Level (TCL) by detecting errors in the classification of faults. By combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulators we are able to automatically generate a Test Environment that enables the validation of the tools and provides supplementary information about the design behavior. Our results showed fault detection rates above 99% including information to improve ISO26262 metrics calculation

Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.