Memristive crossbars are attractive for in-memory computing due to their integration density combined with compute and storage capabilities of their basic devices. However, yield and fidelity of emerging memristive technologies can make their reliable operation unattainable, thus raising interest in simpler topologies. In this paper, we consider synthesis of Boolean functions on 1D memristive line arrays. We propose an optimal procedure that can fully utilize the rich electrical behavior of memristive devices, mixing stateful (resistance-input) and non-stateful (voltage-input) operations as desired by the designer, leveraging their respective strengths. The synthesis method is based on Boolean satisfiability (SAT) solving and supports flexible constraints to enforce, e.g., restrictions of the available peripher-als. We experimentally validate memristive logic circuits beyond individual logic gates by demonstrating the operation of a Galois field multiplier using a 1D line array of 10 memristors in parallel, highlighting the robust performance of our proposed mixed-mode circuit and its synthesis procedure.

Memristive devices can not only be used as nonvolatile memories but also enable computation-in-memory (CIM) computing paradigms. CIM architectures show prospects in significantly reducing the data interaction time and energy consumption between processors and storage, thus addressing the bottleneck problem of the von Neumann architecture. Additionally, the capability of memristive devices to store multiple (resistance) states in one cell offer vast potential for CIM’s multi-valued logic, as they greatly enhance data storage density and computational efficiency. In this study, a novel concept for ternary Łukasiewicz logic utilizing the voltage divider of two (anti-)serially connected memristive devices is proposed. As this approach does not require any switching in the computation process and features a straightforward circuit architecture, a low energy consumption per operation is achieved. In addition, the concept is crossbar-array compatible. The concept is validated by circuit simulations using the JART VCM v1b model that has been calibrated to experimental data of a Pt/Ta2O5/W memristive device.

Quick progress in memristive technologies has led to their consideration for several potential applications, many of which are security-critical. New possibilities of memristors, including their unique combination of non-volatile storage and compute capabilities, make them particularly attractive to edge applications, which are physically exposed to their users and therefore to potential attackers. Therefore, practical deployment of memristive circuitry for, e.g., cryptographic (sub-)modules or on-chip neural network inference, is only feasible when their vulnerability to physical attacks is understood and addressed. We evaluate experimentally one relevant class of physical attacks, namely side-channel attacks, under varying external conditions, namely temperature and magnetic fields. Using a small cryptographic construction, we evaluate both white-box and black-box attack varieties, using respective cryptanalytic techniques. Our results show that, while non-nominal conditions can complicate attacks, the information leakage remains and the secrets are extractable with additional knowledge about the memristive devices. This suggests the need to consider possible external disturbances during security evaluation.

Memristive technologies offer fascinating opportunities for unconventional computing architectures and emerging applications. While memristive devices have received substantial attention as sources of entropy for security applications, security vulnerabilities of memristive technologies for implementing cryptographic circuits have been largely neglected so far. In this article, we provide the first in-depth analysis of power side-channel analysis against memristive cryptographic implementations based on both: physical experiments and simulations. We show that power consumption models developed for CMOS are not fully adequate for memristive circuits. In particular, the memory effect makes even input-independent initialization cycles vulnerable to attacks that would be fundamentally impossible in CMOS technologies. We propose a memristive-oriented Power Estimation Model (mPEM) integrated into the Stochastic Approach (StA) framework and demonstrate its effectiveness against larger-scale circuits. Finally, we demonstrate that attack countermeasures that were effective for CMOS fail for fundamental reasons in the memristive case.