Qiqi Gu 0002

dblp:250/1108-2 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2026
0009-0008-6605-8615ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021
YearPublicationVenuePosition
2026 SPIDER: Unleashing Sparse Tensor Cores for Stencil Computation via Strided Swapping
abstract
Recent research has focused on accelerating stencil computations by exploiting emerging hardware like Tensor Cores. To leverage these accelerators, the stencil operation must be transformed to matrix multiplications. However, this transformation introduces undesired sparsity into the kernel matrix, leading to significant redundant computation.
Qiqi Gu 0002, Chenpeng Wu, Heng Shi 0005, Jianguo Yao 0002
PPoPP1
2026 Scaling NVMM-based file system on intensive shared file access
Qiqi Gu 0002, Chenpeng Wu, Bingheng Yan, Jianguo Yao 0002
J. Syst. Archit.1
2025 Samoyeds: Accelerating MoE Models with Structured Sparsity Leveraging Sparse Tensor Cores
abstract
The escalating size of Mixture-of-Experts (MoE) based Large Language Models (LLMs) presents significant computational and memory challenges, necessitating innovative solutions to enhance efficiency without compromising model accuracy. Structured sparsity emerges as a compelling strategy to address these challenges by leveraging the emerging sparse computing hardware. Prior works mainly focus on the sparsity in model parameters, neglecting the inherent sparse patterns in activations. This oversight can lead to additional computational costs associated with activations, potentially resulting in suboptimal performance.
Chenpeng Wu, Qiqi Gu 0002, Heng Shi 0005, Jianguo Yao 0002, Haibing Guan
EuroSys2