Multi-core systems are required by digital signal processors (DSP) to support the revolutionary Multiple-Input Multiple-Output (MIMO) imaging radars in the automotive industry. Such multi-core processors for Frequency Modulated Continuous Wave (FMCW) radars require the use of low- footprint accelerators that would reduce the overhead as the system scales up with the antenna density. In this paper, we propose an FFT accelerator, named RbFFT, optimized for the MIMO radar processing chain. The architecture of RbFFT reduces the overhead by re-using existing memory in the processing element (PE), and employs a dual-radix butterfly engine with mixed bit resolution to optimize resources in dense radars. RbFFT reduces area by implementing for the first time ultra-low compression in its dual twiddle factor ROM. RbFFT also innovates with custom fetching and buffering strategies to improve memory-based FFTs while reusing logic to integrate reverse bit ordering, windowing and inverse FFT (IFFT) within the same accelerator passes. The proposed accelerator is implemented in a 25-Core Smart MPSoC in 22FDX using Adaptive Body Biasing (ABB) at 0.6V. Besides RbFFT being pioneer in specialized FFT accelerators for dense MIMO systems, the results also show state-of-the-art improvements via 11% reduction in the normalized energy consumption, 4% reduction in latency, and 11 times area reduction with relation to previous silicon implementations.

After several decades of continuously optimizing computing systems, the Moore's law is reaching its end. However, there is an increasing demand for fast and efficient processing systems that can handle large streams of data while decreasing system footprints. Neuromorphic computing answers this need by creating decentralized architectures that communicate with binary events over time. Despite its rapid growth in the last few years, novel algorithms are needed that can leverage the potential of this emerging computing paradigm and can stimulate the design of advanced neuromorphic chips. In this work, we propose a time-based spiking neural network that is mathematically equivalent to the Fourier transform. We implemented the network in the neuromorphic chip Loihi and conducted experiments on five different real scenarios with an automotive frequency modulated continuous wave radar. Experimental results validate the algorithm, and we hope they prompt the design of ad hoc neuromorphic chips that can improve the efficiency of state-of-the-art digital signal processors and encourage research on neuromorphic computing for signal processing.

The increasing density of Multiple-Input Multiple-Output (MIMO) arrays in imaging radars for the automotive industry demands highly parallel systems with low-footprint accelerators, which would enable the concurrent processing of a high number of virtual channels with a low-latency, and without a high area overhead. In this paper, we design, implement, and test multiple handcrafted compression schemes for Twiddle Factor (TF) Read-Only Memories (ROM), aiming to reduce the footprint of a variable-length and dual-radix Fast Fourier Transform (FFT) accelerator in a Multi-core Digital Signal Processor (DSP) for Frequency Modulated Continuous Wave (FMCW) radars. The compression schemes proposed in this paper involve double delta encoding, Radix-specific address optimizations per port, symmetry inclusion, and exploitation of the bit resolution changes within the radar processing chain. All schemes are verified in an FPGA in terms of logic utilization and quantization using a 77-GHz radar, and implemented in a RISCV-based Processing Element (PE) of a Multi-core DSP with an Adaptive Body Bias (ABB) approach in 22FDX technology for assessing area, leakage, and relative latency savings when compared with a dual-ROM equivalent in the state-of-the-art.

The wearability of emotion classifiers is a must if they are to significantly improve the social integration of patients suffering from neurological disorders. Such wearability requires the use of low-power hardware accelerators that would enable near real-time classification and extended periods of operations. In this paper, we architect, design, implement, and test a handcrafted, hardware Convolutional Neural Network, named BioCNN, optimized for EEG-based emotion detection and other similar bio-medical applications. The architecture of BioCNN is based on aggressive pipelining and hardware parallelism that maximizes resource re-use and minimizes memory footprint. The FEXD and DEAP datasets are used to test the BioCNN prototype that is implemented using the Digilent Atlys Board with a low-cost Spartan-6 FPGA. The experimental results show that BioCNN has a competitive energy efficiency of 11GOps/W, a throughput of 1.65GOps that is in line with the real-time specification of a wearable device, and a latency of less than 1ms, which is much smaller than the 150ms required for human interaction times. Its emotion inference accuracy is competitive with the top software-based emotion detectors.