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Huan-Ching Wang

dblp:250/9045 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator		 0.412019
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference · MICRO 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference accelerator
edge inference accelerator		 0.412019
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference · MICRO 2019
Hardware accelerators and domain-specific architectures
machine learning accelerator		 0.412019
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference · MICRO 2019
Hardware accelerators and domain-specific architectures › accelerator architecture
memory-efficient accelerator design		 0.112019
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference · MICRO 2019

Methods — techniques the papers use, named apart from their topics

block-based parallel processing · 0.4DRAM bandwidth reduction · 0.4
YearPublicationVenuePosition
2019 eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference
abstract
Convolutional neural networks (CNNs) have recently demonstrated superior quality for computational imaging applications. Therefore, they have great potential to revolutionize the image pipelines on cameras and displays. However, it is difficult for conventional CNN accelerators to support ultra-high-resolution videos at the edge due to their considerable DRAM bandwidth and power consumption. Therefore, finding a further memory- and computation-efficient microarchitecture is crucial to speed up this coming revolution.
Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang 0013, Li-De Chen
 MICRO3