S. M. Srinivasavarma Vegesna

dblp:251/3401 · DBLP profile ↗
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4ranked-venue papers
3as first author
3since 2021 · last 2025
0000-0001-7838-9982ORCID · reported

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Systems, architecture and hardware · 4 · 3 first-author · 3 since 2021
YearPublicationVenuePosition
2025 Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS
Sameera Shaik, S. M. Srinivasavarma Vegesna, Sk. Noor Mahammad
Integr.2
2022 Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiers
S. M. Srinivasavarma Vegesna, Shanmukha Rao Pydi, Sk. Noor Mahammad
J. Supercomput.1
2021 A TCAM-based Caching Architecture Framework for Packet Classification
abstract
Packet Classification is the enabling function for performing many networking applications like Integrated Services, Differentiated Services, Access Control/Firewalls, and Intrusion Detection. To cope with high-speed links and ever-increasing bandwidth requirements, time-efficient solutions are needed for which Ternary Content Addressable Memories (TCAMs) are popularly used. However, high cost, heavy power consumption, and poor scalability limit their use in many commercial switches. In this work, an efficient framework for caching the packet classification rules on TCAMs in accordance with traffic characteristics is proposed. The proposed design will have a two-level classification engine in which level-1 is a TCAM classifier with a smaller rule capacity and level-2 is a software classifier. The classifiers are assisted by a rule update engine that monitors the rule temporal behavior and performs timely updates of the rules onto level-1. Crucial challenges with respect to the proposed framework design are defined and addressed effectively in this work. Simulation results shows that the architecture can achieve a throughput of 250 Gbps on average by caching only 10% of the total rules for rule databases of sizes 10,000. The proposed architecture, to the best of our knowledge, is the only traffic-aware architecture using TCAMs that provides a completely deployable framework and also can scale for speeds beyond 250 Gbps (OC-1920 and beyond).
S. M. Srinivasavarma Vegesna, Shiv Vidhyut, Sk. Noor Mahammad
ACM Trans. Embed. Comput. Syst.1
2019 A Novel Rule Mapping on TCAM for Power Efficient Packet Classification
abstract
Packet Classification is the enabling function performed in commodity switches for providing various services such as access control, intrusion detection, load balancing, and so on. Ternary Content Addressable Memories (TCAMs) are the de facto standard for performing packet classification at high speeds. However, TCAMs are highly costlier both in terms of cost and power consumption, forcing the switch vendors towards placing lots of effort for power management. Hence, power-efficient solutions for TCAM-based packet classification are highly relevant even today. In this article, we propose a novel rule placement algorithm based on the unique field values’ presence within the rule databases. We evaluate the total search that is needed to be inspected with respect to the traditional placement approach and the proposed placement approach based on the information content within the fields. Simulation results showed an average reduction of 30.55% in the search space by the proposed placement approach, thereby resulting in an average reduction of 18.85% per search energy over TCAM. With typical TCAM clock speeds ranging between 200--400MHz, this reduction in the per-search energy maps to a huge reduction in the total energy consumed by the TCAM-based network switches. The proposed solution is plug-and-play type requiring only minimal pre-processing within the Network Processing Unit (NPU) of the switches and edge routers.
S. M. Srinivasavarma Vegesna, Ashok Chakravarthy Nara, Sk. Noor Mahammad
ACM Trans. Design Autom. Electr. Syst.1