Hardware accelerator-based CNN inference improves the performance and latency but increases the time-to-market. As a result, CNN deployment on hardware is often outsourced to untrusted third parties (3Ps) with security risks, like hardware Trojans (HTs). Therefore, during the outsourcing, designers conceal the information about initial and final CNN layers from 3Ps. However, this paper shows that this solution is ineffective by proposing a hardware-intrinsic attack (HIA), Layer-based Noise Injection (LaBaNI), which successfully performs misclassification without knowing the initial and final layers. LaBaNi uses the statistical properties of feature maps of the CNN to design the trigger with a very low triggering probability and a payload for misclassification. To show the effectiveness of LaBaNI, we demonstrated it on LeNet and LeNet-3D CNN models deployed on Xilinx's PYNQ board. In the experimental results, the attack is successful, non-periodic, and random, hence difficult to detect. Results show that LaBaNI utilizes up to 4% extra LUTs, 5% extra DSPs, and 2% extra FFs, respectively.

Deep learning applications have achieved great success in numerous real-world applications. Deep learning models, especially Convolution Neural Networks (CNN) are often prototyped using FPGA because it offers high power efficiency, and reconfigurability. The deployment of CNNs on FPGAs follows a design cycle that requires saving of model parameters in the on-chip memory during High level synthesis (HLS). Recent advances in edge intelligence requires CNN inference on edge network to increase throughput and reduce latency. To provide flexibility, dynamic parameter allocation to different mobile devices is required to implement either a predefined or defined on-the-fly CNN architecture. In this study, we present novel methodologies for dynamically streaming the model parameters at run-time to implement a traditional CNN architecture. We further propose a library-based approach to design scalable and dynamic distributed CNN inference on the fly leveraging partial-reconfiguration techniques, which is particularly suitable for resource constrained edge devices. The proposed techniques are implemented on the Xilinx PYNQ-Z2 board to prove the concept by utilizing the LeNet-5 CNN model. The results show that the proposed methodologies are effective, with classification accuracy rates of 92%, 86% and 94% respectively.

Security of inference phase deployment of Convolutional neural network (CNN) into resource constrained embedded systems (e.g. low end FPGAs) is a growing research area. Using secure practices, third party FPGA designers can be provided with no knowledge of initial and final classification layers. In this work, we demonstrate that hardware intrinsic attack (HIA) in such a "secure" design is still possible. Proposed HIA is inserted inside mathematical operations of individual layers of CNN, which propagates erroneous operations in all the subsequent CNN layers that leads to misclassification. The attack is non-periodic and completely random, hence it becomes difficult to detect. Five different attack scenarios with respect to each CNN layer are designed and evaluated based on the overhead resources and the rate of triggering in comparison to the original implementation. Our results for two CNN architectures show that in all the attack scenarios, additional latency is negligible (<; 0.61%), increment in DSP, LUT, FF is also less than 2.36%. Three attack scenarios does not require any additional BRAM resources, while in two scenarios BRAM increases, which compensates with the corresponding decrease in FF and LUTs. To the authors' best knowledge this work is the first to address the hardware intrinsic CNN attack with attacker does not have knowledge of the full CNN.

Competition and collaboration are two universal ingredients in all human cultures. Competition has been observed over time as a phenomenon that has helped people achieve the very best of their potentials in their various fields. Competition has also helped individuals achieve feats they would not have ordinarily achieved as they are pushed beyond their limits. The same can also be said of cooperation and collaboration, which can be used to achieve specific goals or objectives. Hence, both competition and collaboration can be vital in creating a healthy learning process among students. This paper discusses a competitive and collaborative platform on the learning process for two selected online courses in Electrical Engineering. Using a platform developed in LabVIEW programming language, a community of students were encouraged to compete online as they try to reduce block diagrams of subsystems in Control Engineering as well as reduce given Series-Parallel Resistor Circuits in the shortest time and amount of steps possible. At the end of each trial, students can view the finish time of other students and can share, online, their individual solutions with the community as well as discuss ideas such as reduction techniques they find most expedient via a public online notepad. This creates a means of learning from the community. The platform helps to passively induce a competitive and collaborative perspective in the learning pathway of students, thereby improving the interest and experience of students in the selected subject areas. The platform uses an online server to maintain communications from all the students in their various locations. Students can view the timed performance of their counterparts on a leadership board thereby engendering induced competition in the learning community. The instructor or administrator can also monitor activities in the community from a server portal.