This brief presents a digital calibration for pipelined analog-to-digital converters (ADCs) utilizing the cascaded nonlinearity correction (CNC) method. By cascading three correction layers for compensating nonlinearities in different parts of pipelined ADC, it comprehensively calibrates distortion in both ADC front end and back end with a low hardware cost. In addition, this work employs a discriminative fine-tuning least-mean-square (DFT-LMS) algorithm with varying step sizes for different layers, thereby improving both the convergence speed and the accuracy. An 800-MS/s, 12-bit ring amplifier-based pipelined ADC is presented to verify the proposed calibration technique. With calibration, the SFDR has a 26.7-dB improvement at low frequency and 23.6-dB improvement at Nyquist frequency, resulting in over 6-dB improvement compared with prior-art calibration techniques. The calibration algorithm has been verified on a TSMC 28-nm CMOS process. The experimental results show that the proposed ADC calibrator has an area of$6592~\mu $m2 and consumes 5.31 mW at 800-MHz clock rate.

A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidth and superior power efficiency over conventional operational amplifier. A high linearity front-end is proposed to mitigate the non-linearity of the ESD diode and provide sufficient driving ability. In addition, it can reject the kickback noise from the core ADC. A digital background calibration method with digital-mixing is adopted to fix the mismatches among channels. The measured SNDR/SFDR with a low-frequency of the prototype ADC are 51.0/68.0 dB, achieving a competitive FoMwof 0.48 pJ/conv.-step at 2.5 GS/s.

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.